HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 727

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

DMA destination address registers 0−7 (DAR0−DAR7) are 32-bit readable/writable registers that
specify the destination address for a DMA transfer. The functions of these registers are the same
as on the SH7750 and SH7750S. For more information, see section 14.2.2, DMA Destination
Address Registers 0−3 (DAR0−DAR3).
14.7.3
Initial value:
Initial value:
DMA transfer count registers 0−7 (DMATCR0−DMATCR7) are 32-bit readable/writable registers
that specify the number of transfers in transfer operations for the corresponding channel (byte
count, word count, longword count, quadword count, or 32-byte count). Functions of these
registers are the same as the transfer-count registers of the SH7750 or SH7750S. For more
information, see section 14.2.3, DMA Transfer Count Registers 0−3 (DMATCR0−DMATCR3).
14.7.4
Initial value:
Initial value:
R/W:
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/(W) R/W R/(W) R/W
Bit:
Bit:
Bit:
Bit:
DMA Transfer Count Registers 0−7 (DMATCR0−DMATCR7)
DMA Channel Control Registers 0−7 (CHCR0−CHCR7)
SSA2 SSA1 SSA0 STC DSA2 DSA1 DSA0 DTC
DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0
31
15
—
31
15
R
0
0
0
30
14
30
14
—
R
0
0
0
29
13
29
13
—
R
0
0
0
28
12
28
12
—
R
0
0
0
27
11
27
11
—
R
0
0
0
26
10
26
10
—
R
0
0
0
Section 14 Direct Memory Access Controller (DMAC)
25
25
—
R
0
9
0
9
0
24
24
—
R
0
8
0
8
0
R/W R/W R/W R/W R/W R/W R/W R/W
Rev.7.00 Oct. 10, 2008 Page 641 of 1074
TM
23
23
—
—
—
R
7
0
7
0
TS2 TS1 TS0 QCL
22
—
—
22
—
R
6
0
6
0
21
21
—
—
—
R
5
0
5
0
20
20
—
—
—
R
4
0
4
0
R/W (R/W) R/W (R/W)
DS
19
19
—
—
3
0
3
0
REJ09B0366-0700
RL
18
18
—
—
IE
2
0
2
0
AM
TE
17
17
—
—
1
0
1
0
DE
AL
16
16
—
—
0
0
0
0