HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 829

MPU 3V 16K I-TEMP,PB-FREE 208-QF

HD6417750RF240DV

Manufacturer Part Number
HD6417750RF240DV
Description
MPU 3V 16K I-TEMP,PB-FREE 208-QF
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750RF240DV

Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750RF240DV
Manufacturer:
HITACHI
Quantity:
7 287
Bit 1—Receive FIFO Data Full (RDF): Indicates that the received data has been transferred
from SCRSR2 to SCFRDR2, and the number of receive data bytes in SCFRDR2 is equal to or
greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control
register (SCFCR2).
Bit 1: RDF
0
1
Note:
*
SCFRDR2 is a 16-byte FIFO register. When RDF = 1, at least the receive trigger set
number of data bytes can be read. If all the data in SCFRDR2 is read and another read
is performed, the data value will be undefined. The number of receive data bytes in
SCFRDR2 is indicated by the lower bits of SCFDR2.
Description
The number of receive data bytes in SCFRDR2 is less than the receive
trigger set number
[Clearing conditions]
The number of receive data bytes in SCFRDR2 is equal to or greater than
the receive trigger set number
[Setting condition]
When SCFRDR2 contains at least the receive trigger set number of receive
data bytes*
Power-on reset or manual reset
When SCFRDR2 is read until the number of receive data bytes in
SCFRDR2 falls below the receive trigger set number after reading RDF
= 1, and 0 is written to RDF
When SCFRDR2 is read by the DMAC until the number of receive data
bytes in SCFRDR2 falls below the receive trigger set number
Section 16 Serial Communication Interface with FIFO (SCIF)
Rev.7.00 Oct. 10, 2008 Page 743 of 1074
REJ09B0366-0700
(Initial value)

Related parts for HD6417750RF240DV