HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 836

MPU 3V 16K I-TEMP,PB-FREE 208-QF

HD6417750RF240DV

Manufacturer Part Number
HD6417750RF240DV
Description
MPU 3V 16K I-TEMP,PB-FREE 208-QF
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750RF240DV

Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750RF240DV
Manufacturer:
HITACHI
Quantity:
7 287
Section 16 Serial Communication Interface with FIFO (SCIF)
16.2.11 Serial Port Register (SCSPTR2)
SCSPTR2 is a 16-bit readable/writable register that controls input/output and data for the port pins
multiplexed with the serial communication interface (SCIF) pins. Input data can be read from the
RxD2 pin, output data written to the TxD2 pin, and breaks in serial transmission/reception
controlled, by means of bits 1 and 0. Data can be read from, and output data written to, the CTS2
pin by means of bits 5 and 4. Data can be read from, and output data written to, the RTS2 pin by
means of bits 6 and 7.
SCSPTR2 can be read or written to by the CPU at all times. All SCSPTR2 bits except bits 6, 4,
and 0 are initialized to 0 by a power-on reset or manual reset; the value of bits 6, 4, and 0 is
undefined. SCSPTR2 is not initialized in standby mode or in the module standby state.
Bits 15 to 8—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 7—Serial Port RTS Port I/O (RTSIO): Specifies the serial port RTS2 pin input/output
condition. When the RTS2 pin is actually set as a port output pin and outputs the value set by the
RTSDT bit, the MCE bit in SCFCR2 should be cleared to 0.
Bit 7: RTSIO
0
1
Rev.7.00 Oct. 10, 2008 Page 750 of 1074
REJ09B0366-0700
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
RTSIO
Description
RTSDT bit value is not output to RTS2 pin
RTSDT bit value is output to RTS2 pin
R/W
15
R
0
7
0
RTSDT
R/W
14
R
0
6
CTSIO
R/W
13
R
0
5
0
CTSDT
R/W
12
R
0
4
11
R
R
0
3
0
10
R
R
0
2
SPB2IO SPB2DT
R/W
R
9
0
1
0
(Initial value)
R/W
R
8
0
0

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