HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 640

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 14 Direct Memory Access Controller (DMAC)
14.2.3
DMA transfer count registers 0–3 (DMATCR0–DMATCR3) are 32-bit readable/writable registers
that specify the transfer count for the corresponding channel (byte count, word count, longword
count, quadword count, or 32-byte count). Specifying H'000001 gives a transfer count of 1, while
H'000000 gives the maximum setting, 16,777,216 (16M) transfers. During DMAC operation, the
remaining number of transfers is shown.
Bits 31–24 of these registers are reserved; they are always read as 0, and should only be written
with 0.
The initial value of these registers after a power-on or manual reset is undefined. They retain their
values in standby mode and deep sleep mode.
In DDT mode, settings to DMATCR0[7:0] may be made from DTR format [55:48] as well. For
details, see Data Transfer Request Format in section 14.5.2, Pin in DDT Mode.
Rev.7.00 Oct. 10, 2008 Page 554 of 1074
REJ09B0366-0700
Initial value:
Initial value:
Initial value:
Initial value:
DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3)
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
R/W
R/W
R/W
31
23
15
—
—
—
R
0
7
R/W
R/W
R/W
30
22
14
—
—
—
R
0
6
R/W
R/W
R/W
29
21
13
—
—
—
R
0
5
R/W
R/W
R/W
28
20
12
—
—
—
R
0
4
R/W
R/W
R/W
27
19
11
—
—
—
R
0
3
R/W
R/W
R/W
26
18
10
—
—
—
R
0
2
R/W
R/W
R/W
25
17
—
—
—
R
0
9
1
R/W
R/W
R/W
24
16
—
—
—
R
0
8
0