HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 444

MPU 3V 16K I-TEMP,PB-FREE 208-QF

HD6417750RF240DV

Manufacturer Part Number
HD6417750RF240DV
Description
MPU 3V 16K I-TEMP,PB-FREE 208-QF
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750RF240DV

Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

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Part Number:
HD6417750RF240DV
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Section 13 Bus State Controller (BSC)
• Synchronous DRAM interface
• Burst ROM interface
• MPX interface
• Byte control SRAM interface
• PCMCIA interface
• Fine refreshing control
• Refresh counter can be used as interval timer
Rev.7.00 Oct. 10, 2008 Page 358 of 1074
REJ09B0366-0700
⎯ 8-CAS byte control for power-down operation
⎯ DRAM control signal timing can be controlled by register settings
⎯ Consecutive accesses to the same row address
⎯ Row address/column address multiplexing according to synchronous DRAM capacity
⎯ Burst operation
⎯ Auto-refresh and self-refresh
⎯ Synchronous DRAM control signal timing can be controlled by register settings
⎯ Consecutive accesses to the same row address
⎯ Wait state insertion can be controlled by program
⎯ Burst operation, executing the number of transfers set in a register
⎯ Address/data multiplexing
⎯ SRAM interface with byte control
⎯ Wait state insertion can be controlled by program
⎯ Bus sizing function for I/O bus width
⎯ Supports refresh operation immediately after self-refresh operation in low-power DRAM
⎯ Interrupt request generated by compare-match
⎯ Interrupt request generated by refresh counter overflow
Connectable areas: 2, 3
Settable bus widths: 64, 32, 16
Connectable areas: 2, 3
Settable bus widths: 64, 32
Connectable areas: 0, 5, 6
Settable bus widths: 64*, 32, 16, 8
Connectable areas: 0 to 6
Settable bus widths: 64, 32
Connectable areas: 1, 4
Settable bus widths: 64, 32, 16
by means of refresh counter overflow interrupt function

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