HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 622

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 Bus State Controller (BSC)
13.3.11 Bus Arbitration
This LSI is provided with a bus arbitration function that grants the bus to an external device when
it makes a bus request.
There are three bus arbitration modes: master mode, partial-sharing master mode, and slave mode.
In master mode the bus is held on a constant basis, and is released to another device in response to
a bus request. In slave mode the bus is not held on a constant basis; a bus request is issued each
time an external bus cycle occurs, and the bus is released again at the end of the access. In partial-
sharing master mode, only area 2 is shared with external devices; slave mode is in effect for area
2, while for other spaces, bus arbitration is not performed and the bus is held constantly. The area
in the master mode chip to which area 2 in the partial-sharing master mode chip is allocated is
determined by an external circuit.
Master mode and slave mode can be specified by the external mode pins. Partial-sharing master
mode is entered from master mode by means of a software setting. See Appendix C, Mode Pin
Settings, for the external mode pin settings. In master mode and slave mode, the bus goes to the
high-impedance state when not being held. In partial-sharing master mode, the bus is constantly
driven, and therefore an external buffer is necessary for connection to the master bus. In master
mode, it is possible to connect an external device that issues bus requests instead of a slave mode
chip. In the following description, an external device that issues bus requests is also referred to as
a slave.
This LSI has two internal bus masters: the CPU and the DMAC. When synchronous DRAM or
DRAM is connected and refresh control is performed, refresh requests constitute a third bus
master. In addition to these are bus requests from external devices in master mode. If requests
occur simultaneously, priority is given, in high-to-low order, to a bus request from an external
device, a refresh request, the DMAC, and the CPU.
To prevent incorrect operation of connected devices when the bus is transferred between master
and slave, all bus control signals are negated before the bus is released. When mastership of the
bus is received, also, bus control signals begin driving the bus from the negated state. Since
signals are driven to the same value by the master and slave exchanging the bus, output buffer
collisions can be avoided.
Bus transfer is executed between bus cycles.
When the bus release request signal (BREQ) is asserted, this LSI releases the bus as soon as the
currently executing bus cycle ends, and outputs the bus use permission signal (BACK). However,
bus release is not performed during multiple bus cycles generated because the data bus width is
smaller than the access size (for example, when performing longword access to 8-bit bus width
Rev.7.00 Oct. 10, 2008 Page 536 of 1074
REJ09B0366-0700