HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 805

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Table 15.13 SCSSR1 Status Flags and Transfer of Receive Data
Receive Errors
Overrun error
Framing error
Parity error
Overrun error + framing error
Overrun error + parity error
Framing error + parity error
Overrun error + framing error +
parity error
Legend:
O: Receive data is transferred from SCRSR1 to SCRDR1.
X: Receive data is not transferred from SCRSR1 to SCRDR1.
Break Detection and Processing: Break signals can be detected by reading the RxD pin directly
when a framing error (FER) is detected. In the break state the input from the RxD pin consists of
all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Note that the SCI
receiver continues to operate in the break state, so if the FER flag is cleared to 0 it will be set to 1
again.
Sending a Break Signal: The input/output condition and level of the TxD pin are determined by
bits SPB0IO and SPB0DT in the serial port register (SCSPTR1). This feature can be used to send
a break signal.
After the serial transmitter is initialized, the TxD pin function is not selected and the value of the
SPB0DT bit substitutes for the mark state until the TE bit is set to 1 (i.e. transmission is enabled).
The SPB0IO and SPB0DT bits should therefore be set to 1 (designating output and high level)
beforehand.
To send a break signal during serial transmission, clear the SPB0DT bit to 0 (designating low
level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the
transmitter is initialized regardless of its current state, and the TxD pin becomes an output port
outputting the value 0.
RDRF
1
0
0
1
1
0
1
SCSSR1 Status Flags
ORER
1
0
0
1
1
0
1
Section 15 Serial Communication Interface (SCI)
Rev.7.00 Oct. 10, 2008 Page 719 of 1074
FER
0
1
0
1
0
1
1
PER
0
0
1
0
1
1
1
Receive Data
Transfer
SCRSR1 → SCRDR1
X
O
O
X
X
O
X
REJ09B0366-0700