HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 671

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Note: When channel 1 is in level-sensing burst mode with the settings shown in figure 14.11, the
14.3.5
Number of States in Bus Cycle: The number of states in the bus cycle when the DMAC is the
bus master is controlled by the bus state controller (BSC) just as it is when the CPU is the bus
master. See section 13, Bus State Controller (BSC), for details.
DREQ Pin Sampling Timing: In external request mode, the DREQ pin is sampled at the rising
edge of CKIO clock pulses. When DREQ input is detected, a DMAC bus cycle is generated and
DMA transfer executed after four CKIO cycles at the earliest.
When falling edge detection is selected for DREQ, the DMAC will recognize DREQ two cycles
(CKIO) later because the signal must pass through the asynchronous input synchronization circuit.
(There is a 1-cycle (CKIO) delay when low-level detection is selected.)
The second and subsequent DREQ sampling operations are performed one cycle after the start of
the first DMAC transfer bus cycle (in the case of single address mode).
DRAK is output for one cycle only, once each time DREQ is detected, regardless of the transfer
mode or DREQ detection method. In the case of burst mode edge detection, DREQ is sampled in
the first cycle only, and so DRAK is output in the first cycle only .
Legend:
Priority system: Round robin mode
Channel 0:
Channel 1:
CPU
CPU
bus is passed to the CPU during a break in requests.
Number of Bus Cycle States and DREQ Pin Sampling Timing
Figure 14.11 Bus Handling with Two DMAC Channels Operating
DMAC CH1
DMAC channel 1
burst mode
Cycle steal mode
Burst mode (edge-sensing)
DMAC CH1
DMAC CH0
CH0
DMAC channel 0 and
channel 1 round robin
mode
Section 14 Direct Memory Access Controller (DMAC)
DMAC CH1
CH1
Rev.7.00 Oct. 10, 2008 Page 585 of 1074
DMAC CH0
CH0
DMAC CH1
DMAC channel 1
burst mode
DMAC CH1
REJ09B0366-0700
CPU
CPU