HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 723

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Table 14.12 DMAC Pins in DDT Mode
Pin Name
Data bus request
Data bus available
Transfer request signal
DMAC strobe
Channel number
notification
Requests for DMA transfer from external devices are normally accepted only on channel 0
(DREQ0) and channel 1 (DREQ1). In DDT mode, the BAVL pin functions as both the data-bus-
available pin and channel-number-notification (ID2) pin.
14.6.3
Table 14.13 shows the configuration of the DMAC's registers. The DMAC of the SH7750R has a
total of 33 registers: four registers are assigned to each channel, and there is a control register for
the overall control of the DMAC.
Register Configuration (SH7750R)
Abbreviation
DBREQ
(DREQ0)
BAVL/ID2
(DRAK0)
TR
(DREQ1)
TDACK
(DACK0)
ID[1:0]
(DRAK1, DACK1)
Section 14 Direct Memory Access Controller (DMAC)
I/O
Input
Output
Input
Output
Output
Rev.7.00 Oct. 10, 2008 Page 637 of 1074
Function
Data bus release request from external
device for DTR format input
Data bus release notification
Data bus can be used 2 cycles after
BAVL is asserted
Notification of channel number to
external device at same time as TDACK
output
If asserted 2 cycles after BAVL
assertion, DTR format is sent
Only TR asserted: DMA request
DBREQ and TR asserted
simultaneously: Direct request to
channel 2
Reply strobe signal for external device
from DMAC
Notification of channel number to
external device at same time as TDACK
output
(ID [1] = DRAK1, ID [0] = DACK1)
REJ09B0366-0700