HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 692

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 14 Direct Memory Access Controller (DMAC)
• TDACK: Reply strobe signal for external device from DMAC
• ID1, ID0: Channel number notification signals
Data Transfer Request Format
The data transfer request format (DTR format) consists of 64 bits, with connection to D[63:0]. In
the case of normal data transfer mode (channel 0, except channel 0) and the handshake protocol
using the data bus, the transfer data size, read/write access, channel number, transfer request
mode, number of transfers, and transfer source or transfer destination address are specified. A
specification in bits 47–32 is invalid.
In the SH7750, only single address mode can be set in normal data transfer mode (channel 0).
With the DTR format, DS = (0: MD = 10, 11, 1: MD = 01), RL = 0, AL = 0, DM[1:0] = 01,
SM[1:0] = 01, RS[3:0] = (0010: R/W = 0, 0011: R/W = 1), TM = (0: MD = 11, 1: MD = 01, 10),
TS[2:0] = (SZ), and IE = 0 settings are made in DMA channel control register 0, COUNT is set in
transfer count register 0, and ADDRESS is set in source/destination address register 0. Therefore,
in DDT mode, the above control registers cannot be written to by the CPU, but can be read.
In the SH7750S, DMAC control registers CHCR0, SAR0, DAR0, and DMATCR0 can be written
to and read by the CPU even in normal data transfer mode (channel 0). Caution is necessary in this
case, as a DMAC control register written to by the CPU will be overwritten by a subsequent
transfer request (MD[1:0] = 01, 10, or 11) using the DTR format.
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SZ
⎯ In the case of direct data transfer mode (valid only for channel 2), a direct transfer request
The assert timing of this signal is the same as the DACKn assert timing of the memory
interfaces.
Note that it is a low active signal.
⎯ 00: Channel 0 (means demand data transfer)
⎯ 01: Channel 1
⎯ 10: Channel 2
⎯ 11: Channel 3
can be made to channel 2 by asserting DBREQ and TR simultaneously.
R/W
ID
57
MD
Figure 14.25 Data Transfer Request Format
55
COUNT
48
(Reserved)
31
ADDRESS
0