HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 864

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 17 Smart Card Interface
17.2
Only registers that have been added, and bit functions that have been modified, for the smart card
interface are described here.
17.2.1
SCSCMR1 is an 8-bit readable/writable register that selects the smart card interface function.
SCSCMR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the
module standby state.
Bits 7 to 4 and 1—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion
format.
Bit 3: SDIR
0
1
Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This
function is used together with the bit 3 function for communication with an inverse convention
card. The SINV bit does not affect the logic level of the parity bit. For parity-related setting
procedures, see section 17.3.4, Register Settings.
Bit 2: SINV
0
1
Rev.7.00 Oct. 10, 2008 Page 778 of 1074
REJ09B0366-0700
Initial value:
Register Descriptions
Smart Card Mode Register (SCSCMR1)
R/W:
Bit:
Description
SCTDR1 contents are transmitted LSB-first
Receive data is stored in SCRDR1 LSB-first
SCTDR1 contents are transmitted MSB-first
Receive data is stored in SCRDR1 MSB-first
Description
SCTDR1 contents are transmitted as they are
Receive data is stored in SCRDR1 as it is
SCTDR1 contents are inverted before being transmitted
Receive data is stored in SCRDR1 in inverted form
—
—
—
7
—
—
—
6
—
—
—
5
—
—
—
4
SDIR
R/W
3
0
SINV
R/W
2
0
—
—
—
1
(Initial value)
(Initial value)
SMIF
R/W
0
0