HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 782

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 15 Serial Communication Interface (SCI)
In serial reception, the SCI operates as described below.
1. The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal
2. The received data is stored in SCRSR1 in LSB-to-MSB order.
3. The parity bit and stop bit are received.
Note: No further receive operations can be performed when a receive error has occurred. Also
4. If the EIO bit in SCSPTR1 is cleared to 0 and the RIE bit in SCSCR1 is set to 1 when the
Table 15.11 Receive Error Conditions
Receive Error
Overrun error
Framing error
Parity error
Rev.7.00 Oct. 10, 2008 Page 696 of 1074
REJ09B0366-0700
synchronization and starts reception.
After receiving these bits, the SCI carries out the following checks.
a. Parity check: The SCI checks whether the number of 1-bits in the receive data agrees with
b. Stop bit check: The SCI checks whether the stop bit is 1. If there are two stop bits, only the
c. Status check: The SCI checks whether the RDRF flag is 0, indicating that the receive data
If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in
SCRDR1.
If a receive error is detected in the error check, the operation is as shown in table 15.11.
RDRF flag changes to 1, a receive-data-full interrupt (RXI) request is generated.
If the RIE bit in SCSCR1 is set to 1 when the ORER, PER, or FER flag changes to 1, a
receive-error interrupt (ERI) request is generated. A receive-data-full request is always output
to the DMAC when the RDRF flag changes to 1.
the parity (even or odd) set in the O/E bit in SCSMR1.
first is checked.
can be transferred from SCRSR1 to SCRDR1.
note that the RDRF flag is not set to 1 in reception, and so the error flags must be cleared
to 0.
Abbreviation
ORER
FER
PER
Condition
Reception of next data is
completed while RDRF flag
in SCSSR1 is set to 1
Stop bit is 0
Received data parity differs
from that (even or odd) set
in SCSMR1
Data Transfer
Receive data is not transferred
from SCRSR1 to SCRDR1
Receive data is transferred from
SCRSR1 to SCRDR1
Receive data is transferred from
SCRSR1 to SCRDR1