HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 157

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

3.1
3.1.1
The SH-4 can handle 29-bit external memory space from an 8-bit address space identifier and 32-
bit logical (virtual) address space. Address translation from virtual address to physical address is
performed using the memory management unit (MMU) built into the SH-4. The MMU performs
high-speed address translation by caching user-created address translation table information in an
address translation buffer (translation lookaside buffer: TLB). The SH-4 has four instruction TLB
(ITLB) entries and 64 unified TLB (UTLB) entries. UTLB copies are stored in the ITLB by
hardware. A paging system is used for address translation, with support for four page sizes (1, 4,
and 64 Kbytes, and 1 Mbyte). It is possible to set the virtual address space access right and
implement storage protection independently for privileged mode and user mode.
3.1.2
The MMU was conceived as a means of making efficient use of physical memory. As shown in
figure 3.1, when a process is smaller in size than the physical memory, the entire process can be
mapped onto physical memory, but if the process increases in size to the point where it does not fit
into physical memory, it becomes necessary to divide the process into smaller parts, and map the
parts requiring execution onto physical memory on an ad hoc basis ((1)). Having this mapping
onto physical memory executed consciously by the process itself imposes a heavy burden on the
process. The virtual memory system was devised as a means of handling all physical memory
mapping to reduce this burden ((2)). With a virtual memory system, the size of the available
virtual memory is much larger than the actual physical memory, and processes are mapped onto
this virtual memory. Thus processes only have to consider their operation in virtual memory, and
mapping from virtual memory to physical memory is handled by the MMU. The MMU is
normally managed by the OS, and physical memory switching is carried out so as to enable the
virtual memory required by a task to be mapped smoothly onto physical memory. Physical
memory switching is performed via secondary storage, etc.
The virtual memory system that came into being in this way works to best effect in a time sharing
system (TSS) that allows a number of processes to run simultaneously ((3)). Running a number of
processes in a TSS did not increase efficiency since each process had to take account of physical
memory mapping. Efficiency is improved and the load on each process reduced by the use of a
virtual memory system ((4)). In this system, virtual memory is allocated to each process. The task
Overview
Features
Role of the MMU
Section 3 Memory Management Unit (MMU)
Section 3 Memory Management Unit (MMU)
Rev.7.00 Oct. 10, 2008 Page 71 of 1074
REJ09B0366-0700