HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 556

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 Bus State Controller (BSC)
In a synchronous DRAM cycle, the BS signal is asserted for one cycle at the start of the bus cycle.
The access sequence is as follows: in a fill operation in the event of a cache miss, 64-bit boundary
data including the missed data is read first, then 32-byte boundary data including the missed data
is read in wraparound mode.
Single Read: With this LSI, as synchronous DRAM is set to burst read/burst write mode, read
data output continues after the required data has been read. To prevent data collisions, after the
required data is read in Td1, empty read cycles Td2 to Td4 are performed, and this LSI waits for
the end of the synchronous DRAM operation. The BS signal is asserted only in Td1.
When the data width is 64 bits, there are 4 burst transfers in a read. In cache-through and other
DMA read cycles, of cycles Td1 to Td4, BS is asserted and data latched only in the Td1 cycle.
Since such empty cycles increase the memory access time, and tend to reduce program execution
speed and DMA transfer speed, it is important both to avoid unnecessary cache-through area
accesses, and to use a data structure that will allow data to be placed at a 32-byte boundary, and to
be transferred in 32-byte units, when carrying out DMA transfer with synchronous DRAM
specified as the source.
Rev.7.00 Oct. 10, 2008 Page 470 of 1074
REJ09B0366-0700