HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 490

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 Bus State Controller (BSC)
Bits 17 and 16—RAS-CAS Delay (RCD1, RCD0): When the DRAM interface is set, these bits
set the RAS-CAS assertion delay time. When the synchronous DRAM interface is set, these bits
set the bank active-read/write command delay time.
Bit 17: RCD1
0
1
Note:
Bits 15 to 13—Write Precharge Delay (TRWL2–TRWL0): These bits set the synchronous
DRAM write precharge delay time. In auto-precharge mode, they specify the time until the next
bank active command is issued after a write cycle. After a write cycle, the next active command is
not issued for a period equivalent to the setting values of the TPC[2:0] and TRWL[2:0] bits.*
After a write cycle, the next precharge command is not issued for a period of TRWL. This setting
is valid only when synchronous DRAM interface is set.
Note: * For setting values and the period during which no command is issued, see 22.3.3, Bus
Bit 15: TRWL2
0
1
Note:
Rev.7.00 Oct. 10, 2008 Page 404 of 1074
REJ09B0366-0700
*
*
Timing.
Inhibited in RAS down mode.
Inhibited in RAS down mode.
Bit 16: RCD0
0
1
0
1
Bit 14: TRWL1
0
1
0
1
DRAM
2 cycles
3 cycles
4 cycles
5 cycles
Bit 13: TRWL0
0
1
0
1
0
1
0
1
Write Precharge ACT Delay Time
1 (Initial value)
2
3*
4*
5*
Reserved (Setting prohibited)
Reserved (Setting prohibited)
Reserved (Setting prohibited)
Description
Synchronous DRAM
Reserved (Setting prohibited)
2 cycles
3 cycles
4 cycles*