HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 79

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 1 Overview
Table 1.1
Table 1.2
Table 1.3
Table 1.4
Table 1.5
Section 2 Programming Model
Table 2.1
Section 3 Memory Management Unit (MMU)
Table 3.1
Section 4 Caches
Table 4.1
Table 4.2
Table 4.3
Table 4.4
Section 5 Exceptions
Table 5.1
Table 5.2
Table 5.3
Section 6 Floating-Point Unit (FPU)
Table 6.1
Table 6.2
Table 6.3
Table 6.4
Table 6.5
Table 6.6
Table 6.7
Section 7 Instruction Set
Table 7.1
Table 7.2
LSI Features ...........................................................................................................
Pin Functions.......................................................................................................... 14
Pin Functions.......................................................................................................... 24
Pin Functions.......................................................................................................... 32
Pin Functions.......................................................................................................... 42
Initial Register Values ............................................................................................ 55
MMU Registers ...................................................................................................... 74
Cache Features (SH7750, SH7750S)...................................................................... 111
Cache Features (SH7750R) .................................................................................... 112
Features of Store Queues........................................................................................ 112
Cache Control Registers......................................................................................... 113
Exception-Related Registers .................................................................................. 149
Exceptions .............................................................................................................. 152
Types of Reset........................................................................................................ 161
Floating-Point Number Formats and Parameters ................................................... 186
Floating-Point Ranges ............................................................................................ 187
Incorrect Operation Result ..................................................................................... 203
FDIV DRm, DRn (DRn/DRm → DRn) ................................................................ 204
FADD DRm, DRn (DRn + DRm → DRn) FSUB DRm, DRn
(DRn − DRm → DRn) ........................................................................................... 205
FMUL DRm, DRn (DRn*DRm → DRn).............................................................. 205
TRAP Routine Processing...................................................................................... 207
Addressing Modes and Effective Addresses .......................................................... 211
Notation Used in Instruction List ........................................................................... 215
Tables
Rev.7.00 Oct. 10, 2008 Page lxxvii of lxxxiv
REJ09B0366-0700
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