HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 746

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 15 Serial Communication Interface (SCI)
15.2.2
SCRDR1 is the register that stores received serial data.
When the SCI has received one byte of serial data, it transfers the received data from SCRSR1 to
SCRDR1 where it is stored, and completes the receive operation. SCRSR1 is then enabled for
reception.
Since SCRSR1 and SCRDR1 function as a double buffer in this way, it is possible to receive data
continuously.
SCRDR1 is a read-only register, and cannot be written to by the CPU.
SCRDR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the
module standby state.
15.2.3
SCTSR1 is the register used to transmit serial data.
To perform serial data transmission, the SCI first transfers transmit data from SCTDR1 to
SCTSR1, then sends the data to the TxD pin starting with the LSB (bit 0).
When transmission of one byte is completed, the next transmit data is transferred from SCTDR1
to SCTSR1, and transmission started, automatically. However, data transfer from SCTDR1 to
SCTSR1 is not performed if the TDRE flag in the serial status register (SCSSR1) is set to 1.
SCTSR1 cannot be directly read or written to by the CPU.
Rev.7.00 Oct. 10, 2008 Page 660 of 1074
REJ09B0366-0700
Initial value:
Receive Data Register (SCRDR1)
Transmit Shift Register (SCTSR1)
R/W:
R/W:
Bit:
Bit:
—
R
7
0
7
—
R
6
0
6
—
R
5
0
5
—
R
4
0
4
—
R
3
0
3
—
R
2
0
2
—
R
1
0
1
—
R
0
0
0