HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 268

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 5 Exceptions
5.7
1. Return from exception handling
2. If a general exception or interrupt occurs when SR.BL = 1
3. SPC when an exception occurs
Rev.7.00 Oct. 10, 2008 Page 182 of 1074
REJ09B0366-0700
If the delay slot instruction has a second data transfer, two checks are performed in step b, as in
1 above.
If the accepted exception (the highest-priority exception) is a delay slot instruction re-
execution type exception, the branch instruction PR register write operation (PC → PR
operation performed in BSR, BSRF, JSR) is inhibited.
a. Check the BL bit in SR with software. If SPC and SSR have been saved to external
b. Issue an RTE instruction. When RTE is executed, the SPC contents are set in PC, the SSR
a. General exception
b. Interrupt
a. Re-execution type general exception
b. Completion type general exception or interrupt
memory, set the BL bit in SR to 1 before restoring them.
contents are set in SR, and branch is made to the SPC address to return from the exception
handling routine.
When a general exception other than a user break occurs, a manual reset is executed. The
value in EXPEVT at this time is H'0000 0020; the value of the SPC and SSR registers is
undefined.
If an ordinary interrupt occurs, the interrupt request is held pending and is accepted after
the BL bit in SR has been cleared to 0 by software. If a nonmaskable interrupt (NMI)
occurs, it can be held pending or accepted according to the setting made by software. In the
sleep or standby state, however, an interrupt is accepted even if the BL bit in SR is set to 1.
The PC value for the instruction in which the general exception occurred is set in SPC, and
the instruction is re-executed after returning from exception handling. If an exception
occurs in a delay slot instruction, however, the PC value for the delay slot instruction is
saved in SPC regardless of whether or not the preceding delayed branch instruction
condition is satisfied.
The PC value for the instruction following that in which the general exception occurred is
set in SPC. If an exception occurs in a branch instruction with delay slot, however, the PC
value for the branch destination is saved in SPC.
Usage Notes