HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 218

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 4 Caches
1. IC address array read
2. IC address array write (non-associative)
3. IC address array write (associative)
4.5.2
The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification. The entry to be accessed is specified in the address field, and the longword
data to be written is specified in the data field.
Rev.7.00 Oct. 10, 2008 Page 132 of 1074
REJ09B0366-0700
Address field
Legend:
V: Validity bit
A: Association bit
The tag and V bit are read into the data field from the IC entry corresponding to the entry set in
the address field. In a read, associative operation is not performed regardless of whether the
association bit specified in the address field is 1 or 0.
The tag and V bit specified in the data field are written to the IC entry corresponding to the
entry set in the address field. The A bit in the address field should be cleared to 0.
When a write is performed with the A bit in the address field set to 1, the tag stored in the entry
specified in the address field is compared with the tag specified in the data field. If the MMU
is enabled at this time, comparison is performed after the virtual address specified by data field
bits [31:10] has been translated to a physical address using the ITLB. If the addresses match
and the V bit is 1, the V bit specified in the data field is written into the IC entry. In other
cases, no operation is performed. This operation is used to invalidate a specific IC entry. If an
ITLB miss occurs during address translation, or the comparison shows a mismatch, an
interrupt is not generated, no operation is performed, and the write is not executed. If an
instruction TLB multiple hit exception occurs during address translation, processing switches
to the instruction TLB multiple hit exception handling routine.
Data field
: Reserved bits (0 write value, undefined read value)
IC Data Array
31
31
1 1 1 1 0 0 0 0
Figure 4.8 Memory-Mapped IC Address Array
24
23
Tag
13
12
10 9
Entry
5 4 3 2 1 0
A
1 0
V