HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 660

MPU 3V 16K I-TEMP,PB-FREE 208-QF

HD6417750RF240DV

Manufacturer Part Number
HD6417750RF240DV
Description
MPU 3V 16K I-TEMP,PB-FREE 208-QF
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750RF240DV

Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

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Manufacturer
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Price
Part Number:
HD6417750RF240DV
Manufacturer:
HITACHI
Quantity:
7 287
Section 14 Direct Memory Access Controller (DMAC)
Figure 14.4 shows the changes in priority levels when transfer requests are issued simultaneously
for channels 0 and 3, and channel 1 receives a transfer request during a transfer on channel 0. The
operation of the DMAC in this case is as follows.
Rev.7.00 Oct. 10, 2008 Page 574 of 1074
REJ09B0366-0700
Transfer on channel 0
Transfer on channel 1
Transfer on channel 2
Transfer on channel 3
Priority after transfer due to
issuance of a transfer request
for channel 1 only.
Initial priority order
Priority order after transfer
Initial priority order
Priority order after transfer
Initial priority order
Priority order after transfer
Initial priority order
Priority order after transfer
CH0 > CH1 > CH2 > CH3
CH0 > CH1 > CH2 > CH3
CH0 > CH1 > CH2 > CH3
CH0 > CH1 > CH2 > CH3
Figure 14.3 Round Robin Mode
CH0 > CH1 > CH2 > CH3
CH1 > CH2 > CH3 > CH0
CH2 > CH3 > CH0 > CH1
CH3 > CH0 > CH1 > CH2
CH2 > CH3 > CH0 > CH1
Channel 0 is given the lowest
priority.
When channel 1 is given the
lowest priority, the priority of
channel 0, which was higher
than channel 1, is also
shifted simultaneously.
When channel 2 is given the
lowest priority, the priorities of
channels 0 and 1, which were
higher than channel 2, are
also shifted simultaneously. If
there is a transfer request for
channel 1 only immediately
afterward, channel 1 is given
the lowest priority and the
priorities of channels 3 and 0
are simultaneously shifted
down.
No change in priority order

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