HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 880

MPU 3V 16K I-TEMP,PB-FREE 208-QF

HD6417750RF240DV

Manufacturer Part Number
HD6417750RF240DV
Description
MPU 3V 16K I-TEMP,PB-FREE 208-QF
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750RF240DV

Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750RF240DV
Manufacturer:
HITACHI
Quantity:
7 287
Section 17 Smart Card Interface
Serial Data Reception: Data reception in smart card mode uses the same processing procedure as
for the normal SCI. Figure 17.9 shows a sample reception processing flowchart.
1. Perform smart card interface mode initialization as described in Initialization above.
2. Check that the ORER flag and PER flag in SCSSR1 are cleared to 0. If either is set, perform
the appropriate receive error handling, then clear both the ORER and the PER flag to 0.
3. Repeat steps 2 and 3 until it can be confirmed that the RDRF flag is set to 1.
4. Read the receive data from SCRDR1.
5. To continue receiving data, clear the RDRF flag to 0 and go back to step 2.
6. To end reception, clear the RE bit to 0.
With the above processing, interrupt handling is possible.
If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests
are enabled, a receive-data-full interrupt (RXI) request will be generated. If an error occurs in
reception and either the ORER flag or the PER flag is set to 1, a transmit/receive-error interrupt
(ERI) request will be generated.
See Interrupt Operation in section 17.3.6 below for details.
If a parity error occurs during reception and the PER flag is set to 1, the received data is still
transferred to SCRDR1, and therefore this data can be read.
Rev.7.00 Oct. 10, 2008 Page 794 of 1074
REJ09B0366-0700

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