HD6417750RF240DV Renesas Electronics America, HD6417750RF240DV Datasheet - Page 673

• Manufacturer Part Number: HD6417750RF240DV
• Description: MPU 3V 16K I-TEMP,PB-FREE 208-QF
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF240DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

4. Burst Mode, Dual Address Mode, Edge Detection
5. Burst Mode, Single Address Mode, Edge Detection
Suspension of DMA Transfer in Case of DREQ Level Detection
With DREQ level detection in burst mode or cycle steal mode, and in dual address mode or single
address mode, the external device for which DMA transfer is being executed can judge from the
rising edge of CKIO that DARK has been asserted, and suspend DMA transfer by negating
DREQ. In this case, the next DARK signal is not output.
In the example shown in figure 14.20, DMAC transfer begins, at the earliest, four CKIO cycles
after the first sampling operation, and the second sampling operation begins one cycle after the
start of the first DMAC transfer bus cycle.
In single address mode, the DACK signal is output every DMAC transfer cycle.
In figure 14.22, with a 32-byte data size, 64-bit bus width, and SDRAM: row hit write, DMAC
transfer begins, at the earliest, six CKIO cycles after the first sampling operation. The second
sampling operation begins one cycle after DACK is asserted for the first DMAC transfer.
In burst mode using dual address mode and edge detection, DREQ sampling is performed in
the first cycle only.
For example, in the case shown in figure 14.15, DMAC transfer begins, at the earliest, five
CKIO cycles after the first sampling operation. DMAC transfer then continues until the end of
the number of data transfers set in DMATCR. DREQ is not sampled during this time, and
therefore DRAK is output in the first cycle only.
In the case of dual address mode transfer initiated by an external request, the DACK signal can
be output in either the read cycle or the write cycle of the DMAC transfer according to the
specification of the AM bit in CHCR.
In burst mode using single address mode and edge detection, DREQ sampling is performed
only in the first cycle.
For example, in the case shown in figure 14.21, DMAC transfer begins, at the earliest, five
cycles after the first sampling operation. DMAC transfer then continues until the end of the
number of data transfers set in DMATCR. DREQ is not sampled during this time, and
therefore DRAK is output in the first cycle only.
In single address mode, the DACK signal is output every DMAC transfer cycle.
Section 14 Direct Memory Access Controller (DMAC)
Rev.7.00 Oct. 10, 2008 Page 587 of 1074
REJ09B0366-0700