DF3026X25V Renesas Electronics America, DF3026X25V Datasheet - Page 830
![MCU 3V 256K PB-FREE 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
DF3026X25V
Manufacturer Part Number
DF3026X25V
Description
MCU 3V 256K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3026X25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3026X25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 830 of 843
- Download datasheet (5Mb)
Appendix D Pin States
Modes 3 and 4: Figure D.2 is a timing diagram for the case in which
external memory access in mode 3 or 4. As soon as
input state.
The address bus is initialized to the low output level 2.5 clock cycles after the low level of
is sampled. However, when PA
to PB
goes low. Clock pin P6
Mode 5: Figure D.3 is a timing diagram for the case in which
memory access in mode 5. As soon as
R D
Clock pin P6
Rev. 2.00 Sep 20, 2005 page 790 of 800
REJ09B0260-0200
,
H W R
3
P6
RES
Internal reset
signal
A
CS
AS, RD
(read)
HWR, LWR
(write)
D
(write)
I/O port,
PA
CS
are used as CS output pins, they go to the high-impedance state at the same time as
20
15
7
4
0
7
/
/A
to A
to D
to CS
, and
A S
23
7
0
0
/ goes to the output state at the next rise of after
to PA
,
1
R D
L W R
Figure D.2 Reset during Memory Access (Modes 3 and 4)
,
6
/A
H W R
go high, and the address bus and D
21
7
/ goes to the output state at the next rise of after
,
,
L W R
4
to PA
, and
Access to external
T1
6
R E S
C S
are used as address bus pins, or when P8
0
memory
go high, and D
goes low, all ports are initialized to the input state.
T2
R E S
T3
goes low, all ports are initialized to the
15
15
to D
to D
R E S
0
0
go to the high-impedance state.
R E S
go to the high-impedance state.
goes low during an external
High-impedance
High-impedance
R E S
goes low.
goes low during an
R E S
H'00000
3
goes low.
to P8
1
and PB
R E S
R E S
A S
0
,
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