DF3026X25V Renesas Electronics America, DF3026X25V Datasheet - Page 654

MCU 3V 256K PB-FREE 100-TQFP

DF3026X25V

Manufacturer Part Number
DF3026X25V
Description
MCU 3V 256K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of DF3026X25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF3026X25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 21 Electrical Characteristics
Table 21.7 Timing of On-Chip Supporting Modules
Conditions: V
Module
Ports and
TPC
16-bit timer
8-bit timer
SCI
Rev. 2.00 Sep 20, 2005 page 614 of 800
REJ09B0260-0200
T
specifications)
Item
Output data delay time
Input data setup time
Input data hold time
Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock
pulse width
Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock
pulse width
Input clock
cycle
Input clock rise time
Input clock fall time
Input clock pulse width
Transmit data delay time
Receive data setup time
(synchronous)
Receive data
hold time
(synchronous)
a
CC
= –20°C to +75°C (regular specifications), T
= 3.0 to 3.6 V, AV
Single edge
Both edges
Single edge
Both edges
Asynchronous t
Synchronous
Clock input
Clock output
CC
= 3.0 to 3.6 V, V
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PWD
PRS
PRH
TOCD
TICS
TCKS
TCKWH
TCKWL
TOCD
TICS
TCKS
TCKWH
TCKWL
Scyc
SCKr
SCKf
SCKW
TXD
RXS
RXH
REF
Min
50
50
50
50
1.5
2.5
50
50
1.5
2.5
4
6
1.5
1.5
0.4
100
100
0
= 3.0 to AV
a
= –40°C to +85°C (wide-range
Max
50
50
50
0.6
100
CC
, V
Unit
ns
ns
ns
ns
ns
ns
t
t
ns
ns
ns
t
t
t
t
t
t
t
ns
ns
ns
ns
cyc
cyc
cyc
cyc
cyc
cyc
cyc
cyc
Scyc
SS
= AV
Test Conditions
Figure 21.15
Figure 21.16
Figure 21.17
Figure 21.16
Figure 21.17
Figure 21.18
Figure 21.19
SS
= 0 V,

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