DF3026X25V Renesas Electronics America, DF3026X25V Datasheet - Page 357
![MCU 3V 256K PB-FREE 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
DF3026X25V
Manufacturer Part Number
DF3026X25V
Description
MCU 3V 256K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3026X25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3026X25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 357 of 843
- Download datasheet (5Mb)
10.2.5
NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups
1 and 0 (pins TP
specified in TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR. The
address of NDRA differs depending on whether TPC output groups 0 and 1 have the same output
trigger or different output triggers.
NDRA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Same Trigger for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by
the same compare match event, the NDRA address is H'FFFA5. The upper 4 bits belong to group
1 and the lower 4 bits to group 0. Address H'FFFA7 consists entirely of reserved bits that cannot
be modified and always read 1.
Address H'FFFA5
Address H'FFFA7
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Next Data Register A (NDRA)
7
NDR7
to TP
R/W
7
0
—
—
7
1
0
). During TPC output, when an 16-bit timer compare match event
Next data 7 to 4
These bits store the next output
data for TPC output group 1
NDR6
R/W
6
0
—
—
6
1
NDR5
R/W
Section 10 Programmable Timing Pattern Controller (TPC)
5
0
—
—
5
1
NDR4
R/W
Reserved bits
4
0
—
—
4
1
Rev. 2.00 Sep 20, 2005 page 317 of 800
NDR3
R/W
3
0
—
—
3
1
Next data 3 to 0
These bits store the next output
data for TPC output group 0
NDR2
R/W
2
0
—
—
2
1
NDR1
R/W
REJ09B0260-0200
1
0
—
—
1
1
NDR0
R/W
0
0
—
—
0
1
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