DF3026X25V Renesas Electronics America, DF3026X25V Datasheet - Page 118
![MCU 3V 256K PB-FREE 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
DF3026X25V
Manufacturer Part Number
DF3026X25V
Description
MCU 3V 256K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3026X25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3026X25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 118 of 843
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Section 4 Exception Handling
The on-chip supporting modules that can request interrupts are the watchdog timer (WDT), 16-bit
timer, 8-bit timer, serial communication interface (SCI), and A/D converter. Each interrupt source
has a separate vector address.
NMI is the highest-priority interrupt and is always accepted * . Interrupts are controlled by the
interrupt controller. The interrupt controller can assign interrupts other than NMI to two priority
levels, and arbitrate between simultaneous interrupts. Interrupt priorities are assigned in interrupt
priority registers A and B (IPRA and IPRB) in the interrupt controller.
For details on interrupts see section 5, Interrupt Controller.
Note: * In the versions with on-chip flash memory, NMI input is sometimes disabled. For details
4.4
Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is
set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1
in CCR. If the UE bit is 0, the I and UI bits are both set to 1 in CCR. The TRAPA instruction
fetches a start address from a vector table entry corresponding to a vector number from 0 to 3,
which is specified in the instruction code.
Rev. 2.00 Sep 20, 2005 page 78 of 800
REJ09B0260-0200
Note:
see 17.9, NMI Input Disabling Conditions.
Trap Instruction
Numbers in parentheses are the number of interrupt sources.
* When the watchdog timer is used as an interval timer, it generates an interrupt
Interrupts
request at every counter overflow.
Figure 4.5 Interrupt Sources and Number of Interrupts
External interrupts
Internal interrupts
NMI (1)
IRQ to IRQ (6)
WDT * (1)
16-bit timer (9)
8-bit timer (8)
SCI (8)
A/D converter (1)
0
5
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