DF3026X25V Renesas Electronics America, DF3026X25V Datasheet - Page 410
![MCU 3V 256K PB-FREE 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
DF3026X25V
Manufacturer Part Number
DF3026X25V
Description
MCU 3V 256K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3026X25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3026X25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 410 of 843
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Section 12 Serial Communication Interface
Bit 3—Parity Error (PER): Indicates that reception of data with parity added ended abnormally
due to a parity error in asynchronous mode.
Bit 3
PER
0
1
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the PER flag, which retains its previous
Bit 2—Transmit End (TEND): The function of this bit differs for the normal serial
communication interface and for the smart card interface. Its function is switched with the SMIF
bit in SCMR.
Bit 2
TEND
0
1
Rev. 2.00 Sep 20, 2005 page 370 of 800
REJ09B0260-0200
For Serial Communication Interface (SMIF Bit in SCMR Cleared to 0)
Indicates that when the last bit of a serial character was transmitted TDR did not contain valid
transmit data, so transmission has ended. The TEND flag is a read-only bit and cannot be
written.
2. When a parity error occurs the SCI transfers the receive data into RDR but does not set
value.
the RDRF flag. Serial receiving cannot continue while the PER flag is set to 1. In
synchronous mode, serial transmitting is also disabled.
Description
Receiving is in progress or has ended normally *
[Clearing conditions]
The chip is reset or enters standby mode
A receive parity error occurred *
[Setting condition]
The number of 1s in receive data, including the parity bit, does not match the
even or odd parity setting of O/
Description
Transmission is in progress
[Clearing condition]
Read TDRE when TDRE = 1, then write 0 in TDRE
End of transmission
[Setting conditions]
Read PER when PER = 1, then write 0 in PER
The chip is reset or enters standby mode
The TE bit in SCR is cleared to 0
TDRE is 1 when the last bit of a 1-byte serial transmit character is
transmitted
E
2
in SMR
1
(Initial value)
(Initial value)
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