DF3026X25V Renesas Electronics America, DF3026X25V Datasheet - Page 170

• Manufacturer Part Number: DF3026X25V
• Description: MCU 3V 256K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3026X25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller
6.3.5
The H8/3024 Group provides a choice of two address update methods: either the same method as
in the previous H8/300H Series (address update mode 1), or a method in which address updating is
restricted to external space accesses (address update mode 2).
Figure 6.5 shows examples of address output in these two update modes.
Address Update Mode 1: Address update mode 1 is compatible with the previous H8/300H
Series. Addresses are always updated between bus cycles.
Address Update Mode 2: In address update mode 2, address updating is performed only in
external space accesses. In this mode, the address can be retained between an external space read
cycle and an instruction fetch cycle (on-chip memory) by placing the program in on-chip memory.
Address update mode 2 is therefore useful when connecting a device that requires address hold
time with respect to the rise of the
Switching between address update modes 1 and 2 is performed by means of the ADRCTL bit in
ADRCR. The initial value of ADRCR is the address update mode 1 setting, providing
compatibility with the previous H8/300H Series.
Rev. 2.00 Sep 20, 2005 page 130 of 800
REJ09B0260-0200
Address bus
(Address update
mode 1)
Address bus
(Address update
mode 2)
RD
Address Output Method
Figure 6.5 Sample Address Output in Each Address Update Mode
memory cycle
On-chip
(Basic Bus Interface, 3-State Space)
R D
read cycle
External
strobe.
memory cycle
On-chip
read cycle
External
memory cycle
On-chip