DF3026X25V Renesas Electronics America, DF3026X25V Datasheet - Page 200
![MCU 3V 256K PB-FREE 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
DF3026X25V
Manufacturer Part Number
DF3026X25V
Description
MCU 3V 256K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3026X25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3026X25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 200 of 843
- Download datasheet (5Mb)
Section 7 I/O Ports
In modes 5 to 7, P2DDR is a write-only register. Its value cannot be read. All bits return 1 when
read.
P2DDR is initialized to H'FF in modes 1 to 4, and to H'00 in modes 5 to 7, by a reset and in
hardware standby mode. In software standby mode it retains its previous setting. Therefore, if a
transition is made to software standby mode while port 2 is functioning as an input/output port and
a P2DDR bit is set to 1, the corresponding pin maintains its output state.
Port 2 Data Register (P2DR): P2DR is an 8-bit readable/writable register that stores output data
for Port 2. When port 2 functions as an output port, the value of this register is output. When a bit
in P2DDR is set to 1, if port 2 is read the value of the corresponding P2DR bit is returned. When a
bit in P2DDR is cleared to 0, if port 2 is read the corresponding pin logic level is read.
P2DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Port 2 Input Pull-Up MOS Control Register (P2PCR): P2PCR is an 8-bit readable/writable
register that controls the MOS input pull-up transistors in port 2.
In modes 5 to 7, when a P2DDR bit is cleared to 0 (selecting generic input), if the corresponding
bit in P2PCR is set to 1, the input pull-up transistor is turned on.
P2PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Rev. 2.00 Sep 20, 2005 page 160 of 800
REJ09B0260-0200
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
P2 PCR
R/W
R/W
P2
7
7
0
7
0
7
P2 PCR
R/W
R/W
P2
6
6
0
6
0
6
P2 PCR
R/W
R/W
P2
5
Port 2 input pull-up MOS control 7 to 0
These bits control input pull-up
transistors built into port 2
5
0
5
0
Port 2 data 7 to 0
These bits store data for port 2 pins
5
P2 PCR
R/W
R/W
P2
4
4
0
4
0
4
P2 PCR
R/W
R/W
P2
3
3
0
3
0
3
P2 PCR
R/W
R/W
P2
2
2
0
2
0
2
P2 PCR
R/W
R/W
P2
1
1
0
1
0
1
P2 PCR
R/W
R/W
P2
0
0
0
0
0
0
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