DF3026X25V Renesas Electronics America, DF3026X25V Datasheet - Page 185
![MCU 3V 256K PB-FREE 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
DF3026X25V
Manufacturer Part Number
DF3026X25V
Description
MCU 3V 256K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3026X25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3026X25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 185 of 843
- Download datasheet (5Mb)
Usage Note: When non-insertion of an idle cycle is specified, the rise (negation) of
(assertion) of
this case.
If consecutive reads to a different external area occur while the ICIS1 bit in BCR is cleared to 0, or
if an external read is followed by a write cycle for a different external area while the ICIS0 bit is
cleared to 0, negation of
will occur simultaneously. Depending on the output delay time of each signal, therefore, it is
possible that the
bus cycle will overlap.
As long as
non-insertion of an idle cycle can be specified.
Address bus
R D
C S
CSn
and
RD
n
R D
Simultaneous change of RD and
CSn: possibility of mutual overlap
may occur simultaneously. Figure 6.19 shows an example of the operation in
C S
(a) Idle cycle not inserted
low output in the previous read cycle and the
Bus cycle A Bus cycle B
n
T
do not change simultaneously, or if there is no problem even if they do,
1
R D
Figure 6.19 Example of Idle Cycle Operation
T
2
in the first read cycle and assertion of
T
3
T
1
T
2
Address bus
Rev. 2.00 Sep 20, 2005 page 145 of 800
CSn
RD
C S
(b) Idle cycle inserted
Bus cycle A Bus cycle B
C S
T
1
n
n
low output in the following
T
in the following bus cycle
2
Section 6 Bus Controller
T
3
T
REJ09B0260-0200
i
T
1
R D
T
2
and fall
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