DF3026X25V Renesas Electronics America, DF3026X25V Datasheet - Page 638
![MCU 3V 256K PB-FREE 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
DF3026X25V
Manufacturer Part Number
DF3026X25V
Description
MCU 3V 256K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3026X25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3026X25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 20 Power-Down State
20.3
20.3.1
When the SSBY bit is cleared to 0 in SYSCR, execution of the SLEEP instruction causes a
transition from the program execution state to sleep mode. Immediately after executing the SLEEP
instruction the CPU halts, but the contents of its internal registers are retained. On-chip supporting
modules do not halt in sleep mode. Modules which have been placed in standby by the module
standby function, however, remain halted.
20.3.2
Sleep mode is exited by an interrupt, or by input at the
Exit by Interrupt: An interrupt terminates sleep mode and causes a transition to the interrupt
exception handling state. Sleep mode is not exited by an interrupt source in an on-chip supporting
module if the interrupt is disabled in the on-chip supporting module. Sleep mode is not exited by
an interrupt other than NMI if the interrupt is masked by interrupt priority settings and the settings
of the I and UI bits in CCR, IPR.
Exit by
Exit by
mode.
20.4
20.4.1
To enter software standby mode, execute the SLEEP instruction while the SSBY bit is set to 1 in
SYSCR.
In software standby mode, current dissipation is reduced to an extremely low level because the
CPU, clock, and on-chip supporting modules all halt. On-chip supporting modules are reset and
halted. As long as the specified voltage is supplied, however, CPU register contents and on-chip
RAM data are retained. The settings of the I/O ports also held. When the WDT is used as a
watchdog timer (WT/
setting TME to 1, SSBY should be cleared to 0.
Rev. 2.00 Sep 20, 2005 page 598 of 800
REJ09B0260-0200
R E S
S T B Y
Sleep Mode
Transition to Sleep Mode
Exit from Sleep Mode
Software Standby Mode
Transition to Software Standby Mode
Input: Low input at the
Input: Low input at the
I T
= 1), the TME bit must be cleared to 0 before setting SSBY. Also, when
R E S
S T B Y
pin exits from sleep mode to the reset state.
pin exits from sleep mode to hardware standby
R E S
or
S T B Y
pin.
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