DF3026X25V Renesas Electronics America, DF3026X25V Datasheet - Page 136

MCU 3V 256K PB-FREE 100-TQFP

DF3026X25V

Manufacturer Part Number
DF3026X25V
Description
MCU 3V 256K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of DF3026X25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF3026X25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 5 Interrupt Controller
Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF).
Interrupts IRQ
whether the corresponding pin is set for input or output. When using a pin for external interrupt
input, clear its DDR bit to 0 and do not use the pin for chip select output, SCI input/output, or A/D
external trigger input.
5.3.2
Twenty-Seven internal interrupts are requested from the on-chip supporting modules.
5.3.3
Table 5.3 lists the interrupt exception handling sources, their vector addresses, and their default
priority order. In the default priority order, smaller vector numbers have higher priority. The
priority of interrupts other than NMI can be changed in IPRA and IPRB. The priority order after a
reset is the default order shown in table 5.3.
Rev. 2.00 Sep 20, 2005 page 96 of 800
REJ09B0260-0200
Each on-chip supporting module has status flags for indicating interrupt status, and enable bits
for enabling or disabling interrupts.
Interrupt priority levels can be assigned in IPRA and IPRB.
Note: n = 5 to 0
Internal Interrupts
Interrupt Exception Handling Vector Table
IRQn
input pin
IRQnF
0
to IRQ
5
have vector numbers 12 to 17. These interrupts are detected regardless of
Figure 5.3 Timing of Setting of IRQnF

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