DF3026X25V Renesas Electronics America, DF3026X25V Datasheet - Page 216
![MCU 3V 256K PB-FREE 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
DF3026X25V
Manufacturer Part Number
DF3026X25V
Description
MCU 3V 256K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3026X25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3026X25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 216 of 843
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Section 7 I/O Ports
7.8.2
Table 7.12 summarizes the port 7 register. Port 7 is an input port, and port 7 has no data direction
register.
Table 7.12 Port 7 Data Register
Address *
H'FFFD6
Note: * Lower 20 bits of the address in advanced mode.
Port 7 Data Register (P7DR)
When port 7 is read, the pin logic levels are always read. P7DR cannot be modified.
7.9
7.9.1
Port 8 is a 5-bit input/output port that is also used for
A/D converter
In modes 1 to 5 (expanded modes), port 8 can provide
A D T R G
In modes 6 and 7 (single-chip modes), port 8 can provide
See table 7.15 for the selection of pin functions in single-chip mode.
See section 14, A/D Converter, for a description of the A/D converter’s
The
input or output. Caution is therefore required. For details see section 5.3.1, External Interrupts.
Rev. 2.00 Sep 20, 2005 page 176 of 800
REJ09B0260-0200
Bit
Initial value
Read/Write
Note: * Determined by pins P7
I R Q
3
input. See table 7.14 for the selection of pin functions in expanded modes.
Register Description
Port 8
Overview
to
I R Q
A D T R G
Port 7 data register
Name
0
functions are selected by IER settings, regardless of whether the pin is used for
P7
—*
R
7
7
input. Figure 7.8 shows the pin configuration of port 8.
P7
—*
R
6
6
7
to P7
P7
—*
0
R
5
.
5
Abbreviation
P7DR
P7
—*
R
4
4
C S
C S
3
3
I R Q
to
to
P7
—*
R
C S
3
C S
3
3
to
0
0
output,
I R Q
output,
R/W
R
P7
—*
R
0
2
input and
A D T R G
2
I R Q
I R Q
3
3
Initial Value
Undetermined
to
to
P7
—*
R
1
I R Q
input pin.
A D T R G
I R Q
1
0
0
input, and
input, and
P7
—*
R
0
input.
0
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