DF3026X25V Renesas Electronics America, DF3026X25V Datasheet - Page 311
![MCU 3V 256K PB-FREE 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
DF3026X25V
Manufacturer Part Number
DF3026X25V
Description
MCU 3V 256K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3026X25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3026X25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 311 of 843
- Download datasheet (5Mb)
9.1
The H8/3024 Group has a built-in 8-bit timer module with four channels (TMR0, TMR1, TMR2,
and TMR3), based on 8-bit counters. Each channel has an 8-bit timer counter (8TCNT) and two
8-bit time constant registers (TCORA and TCORB) that are constantly compared with the 8TCNT
value to detect compare match events. The timers can be used as multifunctional timers in a
variety of applications, including the generation of a rectangular-wave output with an arbitrary
duty cycle.
9.1.1
The features of the 8-bit timer module are listed below.
Selection of four clock sources
The counters can be driven by one of three internal clock signals ( /8, /64, or /8192) or an
external clock input (enabling use as an external event counter).
Selection of three ways to clear the counters
The counters can be cleared on compare match A or B, or input capture B.
Timer output controlled by two compare match signals
The timer output signal in each channel is controlled by two independent compare match
signals, enabling the timer to generate output waveforms with an arbitrary duty cycle or PWM
output.
A/D converter can be activated by a compare match
Two channels can be cascaded
Input capture function can be set
8-bit or 16-bit input capture operation is available.
Channels 0 and 1 can be operated as the upper and lower halves of a 16-bit timer (16-bit
count mode).
Channels 2 and 3 can be operated as the upper and lower halves of a 16-bit timer (16-bit
count mode).
Channel 1 can count channel 0 compare match events (compare match count mode).
Channel 3 can count channel 2 compare match events (compare match count mode).
Overview
Features
Section 9 8-Bit Timers
Rev. 2.00 Sep 20, 2005 page 271 of 800
Section 9 8-Bit Timers
REJ09B0260-0200
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