DF3026X25V Renesas Electronics America, DF3026X25V Datasheet - Page 538
![MCU 3V 256K PB-FREE 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
DF3026X25V
Manufacturer Part Number
DF3026X25V
Description
MCU 3V 256K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3026X25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3026X25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 538 of 843
- Download datasheet (5Mb)
Section 17 Flash Memory [H8/3026F-ZTAT Version]
6. Boot mode can be entered by setting pins MD
7. If the mode pin input levels are changed (for example, from low to high) during a reset, the
Rev. 2.00 Sep 20, 2005 page 498 of 800
REJ09B0260-0200
(BRR). The transmit data output pin, TxD
P9DDR, P9
The contents of the CPU’s internal general registers are undefined at this time, so these
registers must be initialized immediately after branching to the user program. In particular,
since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be
specified for use by the user program.
The initial values of other on-chip registers are not changed.
setting conditions shown in table 17.6, and then executing a reset-start.
a. When switching from boot mode to normal mode, the boot mode state within the chip must
b. Do not change the input levels of the mode pins (MD
c. The FWE pin must not be driven low while the boot program is running or flash memory is
state of ports with multiplexed address functions and bus control output signals (
L W R
Therefore, care must be taken to make pin settings to prevent these pins from being used
directly as output signal pins during a reset, or to prevent collision with signals outside the
MCU.
first be cleared by reset input via the
20 system clock cycles. *
mode. To change the mode, the
if a watchdog timer reset occurs in the boot mode state, the MCU’s internal state will not
be cleared, and the on-chip boot program will be restarted regardless of the mode pin
states.
being programmed or erased *
,
H W R
1
DR = 1 in P9DR).
) may also change according to the change in the MCU’s operating mode.
H8/3026F-ZTAT
version
3
MD2
MD1
MD0
FWE
RES
CSn
2
.
R E S
R E S
pin must first be driven low to set the reset state. Also,
1
, goes to the high-level output state (P9
pin *
0
to MD
System
control
1
. The
unit
2
and FWE in accordance with the mode
R E S
2
to MD
pin must be held low for at least
0
) or the FWE pin in boot
memory,
External
etc.
C S n
1
DDR = 1 in
,
A S
,
R D
,
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