DF3026X25V Renesas Electronics America, DF3026X25V Datasheet - Page 634
DF3026X25V
Manufacturer Part Number
DF3026X25V
Description
MCU 3V 256K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3026X25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3026X25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 20 Power-Down State
Bit 7—Software Standby (SSBY): Enables transition to software standby mode. When software
standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal
operation. To clear this bit, write 0.
Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU
and on-chip supporting modules wait for the clock to settle when software standby mode is exited
by an external interrupt. If the clock is generated by a crystal resonator, set these bits according to
the clock frequency so that the waiting time will be at least 7 ms. See table 20.3.
If an external clock is used, choose a setting, according to the operating frequency, that gives a
wait time of at least 100 µs.
Bit 1—Software Standby Output Port Enable (SSOE): Specifies whether the address bus and
bus control signals (
placed in the high-impedance state in software standby mode.
Rev. 2.00 Sep 20, 2005 page 594 of 800
REJ09B0260-0200
Bit 7
SSBY
0
1
Bit 6
STS2
0
1
1
1
1
Bit 1
SSOE
0
1
Bit 5
STS1
0
1
0
0
1
1
Description
SLEEP instruction causes transition to sleep mode
SLEEP instruction causes transition to software standby mode
Description
In software standby mode, the address bus and bus control signals are all high-
impedance
In software standby mode, the address bus retains its output state and bus control
signals are fixed high
C S
Bit 4
STS0
0
1
0
1
0
1
0
1
0
to
C S
7
,
Description
Waiting time = 8,192 states
Waiting time = 16,384 states
Waiting time = 32,768 states
Waiting time = 65,536 states
Waiting time = 131,072 states
Waiting time = 262,144 states
Waiting time = 1,024 states
Illegal setting
A S
,
R D
,
H W R
, and
L W R
) are kept as outputs or fixed high, or
(Initial value)
(Initial value)
(Initial value)
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