DF3026X25V Renesas Electronics America, DF3026X25V Datasheet - Page 396
![MCU 3V 256K PB-FREE 100-TQFP](/photos/28/61/286123/100-tqfp__100-vqfp_sml.jpg)
DF3026X25V
Manufacturer Part Number
DF3026X25V
Description
MCU 3V 256K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3026X25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
70
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3026X25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 396 of 843
- Download datasheet (5Mb)
Section 12 Serial Communication Interface
12.2
12.2.1
RSR is the register that receives serial data.
Bit
The SCI loads serial data input at the RxD pin into RSR in the order received, LSB (bit 0) first,
thereby converting the data to parallel data. When one byte of data has been received, it is
automatically transferred to RDR. The CPU cannot read or write RSR directly.
12.2.2
RDR is the register that stores received serial data.
When the SCI has received one byte of serial data, it transfers the received data from RSR into
RDR for storage, completing the receive operation. RSR is then ready to receive the next data.
This double-buffering allows data to be received continuously.
RDR is a read-only register. Its contents cannot be modified by the CPU. RDR is initialized to
H'00 by a reset and in standby mode.
Rev. 2.00 Sep 20, 2005 page 356 of 800
REJ09B0260-0200
Read/Write
Bit
Initial value
Read/Write
Register Descriptions
Receive Shift Register (RSR)
Receive Data Register (RDR)
R
7
0
—
7
R
6
0
—
6
R
0
5
—
5
R
0
4
—
4
R
3
0
—
3
R
0
2
—
2
1
R
0
—
1
—
0
0
R
0
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