AM186ES Advanced Micro Devices, AM186ES Datasheet - Page 99

• Manufacturer Part Number: AM186ES
• Description: microcontrollers provide a low-cost/ high-performance solution for embedded system designers who wish to use the x86 architecture.
• Manufacturer: Advanced Micro Devices

7.2.2
Figure 7-3
Cascade Mode
The Am186ES and Am188ES microcontrollers have seven interrupt pins, two of which
(INT2 and INT3) have dual functions. In fully nested mode, the seven pins are used as
direct interrupt inputs and the corresponding interrupt types are generated internally. In
cascade mode, four of the seven pins can be configured into interrupt input and dedicated
acknowledge signal pairs. INT0 can be configured with interrupt acknowledge INTA0
(INT2). INT1 can be configured with interrupt acknowledge INTA1 (INT3).
External sources in cascade mode use externally generated interrupt types. When an
interrupt is acknowledged, two INTA cycles are initiated and the type is read into the
microcontroller on the second cycle (see Section 7.1.5 on page 7-8). The capability to
interface to one or two external 82C59A programmable interrupt controllers is provided
when the inputs are configured in cascade mode.
Figure 7-3 shows the interconnection for cascade mode. INT0 is an interrupt input interfaced
to one 82C59A, and INT2/INTA0 serves as the dedicated interrupt acknowledge signal to
that peripheral. INT1 and INT3/INTA1 are also interfaced to an 82C59A. Each interrupt and
acknowledge pair can be selectively placed in the cascade or non-cascade mode by
programming the proper value into the INT0 and INT1 control registers. The dedicated
acknowledge signals eliminate the need for external logic to generate INTA and device
select signals.
Cascade mode provides the capability to serve up to 128 external interrupt sources through
the use of external master and slave 82C59As. Three levels of priority are created, requiring
priority resolution in the microcontroller interrupt controller, the master 82C59As, and the
slave 82C59As. If an external interrupt is serviced, one IS bit is set at each of these levels.
When the interrupt service routine is completed, up to three end-of-interrupt (EOI) register
writes must be issued by the program.
Cascade Mode Interrupt Controller Connections
INT4
INT5
INT6
Microcontroller
or Am188ES
Am186ES
INTA0
INT1
INTA1
INT0
V
V
CC
CC
Interrupt Control Unit
82C59A
82C59A
82C59A
82C59A
Interrupt Sources
Interrupt Sources
7-11