AM186ES Advanced Micro Devices, AM186ES Datasheet - Page 82

• Manufacturer Part Number: AM186ES
• Description: microcontrollers provide a low-cost/ high-performance solution for embedded system designers who wish to use the x86 architecture.
• Manufacturer: Advanced Micro Devices

5.5.5
Figure 5-5
5-12
Peripheral Chip Select Register
(PACS, Offset A4h)
Unlike the UCS and LCS chip selects, the PCS outputs assert with the same timing as the
multiplexed AD address bus. Also, each peripheral chip select asserts over a 256-byte
address range, which is twice the address range covered by peripheral chip selects in the
80C186 and 80C188 microcontrollers.
The Am186ES and Am188ES microcontrollers provide six chip selects, PCS6–PCS5 and
PCS3–PCS0, for use within a user-locatable memory or I/O block. (PCS4 is not
implemented on the Am186ES and Am 188ES microcontrollers). The base address of the
memory block can be located anywhere within the 1-Mbyte memory address space,
exclusive of the areas associated with the UCS, LCS, and MCS chip selects, or they can
be configured to access the 64-Kbyte I/O space.
The Peripheral Chip Selects are programmed through two registers—the Peripheral Chip
Select (PACS) register and the PCS and MCS Auxiliary (MPCS) register. The Peripheral
Chip Select (PACS) register (Figure 5-5) determines the base address, the ready condition,
and the wait states for the PCS3–PCS0 outputs.
The PCS and MCS Auxiliary (MPCS) register (see Figure 5-4) contains bits that configure
the PCS6–PCS5 pins as either chip selects or address pins A1 and A2. When the PCS6–
PCS5 pins are chip selects, the MPCS register also determines whether PCS chip selects
are active during memory or I/O bus cycles and specifies the ready and wait states for the
PCS6–PCS5 outputs.
The PCS pins are not active on reset. The PCS pins are activated as chip selects by writing
to the PACS and MPCS registers.
PCS6–PCS5 can be configured and activated as address pins by writing only the MPCS
register. No corresponding access to the PACS register is required in this case.
PCS3–PCS0 can be configured for zero wait states to 15 wait states. PCS6–PCS5 can be
configured for zero wait states to three wait states.
Peripheral Chip Select Register
The value of the PACS register at reset is undefined.
Bits 15–7: Base Address (BA19–BA11)—The base address of the peripheral chip select
block is defined by BA19–BA11 of the PACS register. BA19–BA11 correspond to bits
19–11 of the 20-bit programmable base address of the peripheral chip select block. Bit 6
of the PACS register corresponds to bit 10 of the base address in the original 80C186 and
80C188 microcontrollers and is not implemented. Thus, code previously written for the
80C186 microcontroller in which bit 6 was set with a meaningful value would not produce
the address expected on the Am186ES microcontroller.
When the PCS chip selects are mapped to I/O space, BA19–16 must be programmed to
0000b because the I/O address bus is only 16-bits wide.
15
BA19–BA11
Chip Select Unit
7
1
1 1
R3
R2
R1–R0
0