AM186ES Advanced Micro Devices, AM186ES Datasheet - Page 7

• Manufacturer Part Number: AM186ES
• Description: microcontrollers provide a low-cost/ high-performance solution for embedded system designers who wish to use the x86 architecture.
• Manufacturer: Advanced Micro Devices

CHAPTER 8
CHAPTER 9
CHAPTER 10
8.1
8.2
8.3
9.1
9.2
9.3
9.4
10.1 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.2 PROGRAMMABLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
TIMER CONTROL UNIT
DMA CONTROLLER
ASYNCHRONOUS SERIAL PORTS
7.4.3 Timer and DMA Interrupt Control Registers
7.4.4 Interrupt Status Register (INTSTS, Offset 30h). . . . . . . . . . . . . . 7-30
7.4.5 Interrupt Request Register (REQST, Offset 2Eh) . . . . . . . . . . . . 7-31
7.4.6 Interrupt In-Service Register (INSERV, Offset 2Ch) . . . . . . . . . . 7-32
7.4.7 Priority Mask Register (PRIMSK, Offset 2Ah) . . . . . . . . . . . . . . . 7-33
7.4.8 Interrupt Mask Register (IMASK, Offset 28h) . . . . . . . . . . . . . . . 7-34
7.4.9 Specific End-of-Interrupt Register (EOI, Offset 22h) . . . . . . . . . . 7-35
7.4.10 Interrupt Vector Register (INTVEC, Offset 20h) . . . . . . . . . . . . . 7-36
OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
PULSE WIDTH DEMODULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
PROGRAMMABLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.3.1 Timer Operating Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.3.2 Timer 0 and Timer 1 Mode and Control Registers
8.3.3 Timer 2 Mode and Control Register (T2CON, Offset 66h) . . . . . . 8-5
8.3.4 Timer Count Registers
8.3.5 Timer Maxcount Compare Registers
OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
DMA OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
PROGRAMMABLE DMA REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
9.3.1 DMA Control Registers
9.3.2 Serial Port/DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
9.3.3 DMA Transfer Count Registers
9.3.4 DMA Destination Address High Register (High Order Bits)
9.3.5 DMA Destination Address Low Register (Low Order Bits)
9.3.6 DMA Source Address High Register (High Order Bits)
9.3.7 DMA Source Address Low Register (Low Order Bits)
DMA REQUESTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
9.4.1 Synchronization Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
9.4.2 DMA Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
9.4.3 DMA Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
9.4.4 DMA Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
9.4.5 DMA Channels on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
10.1.1 Serial Port Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.2.1 Serial Port 0/1 Control Registers
10.2.2 Serial Port 0/1 Status Registers
(T0INTCON, Offset 32h, T1INTCON, Offset 38h, T2INTCON,
Offset 3Ah, DMA0CON/INT5, Offset 34h, DMA1CON/INT6,
Offset 36h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-29
(T0CON, Offset 56h, T1CON, Offset 5Eh) . . . . . . . . . . . . . . . . . . 8-3
(T0CNT, Offset 50h, T1CNT, Offset 58h, T2CNT, Offset 60h) . . . 8-6
(T0CMPA, Offset 52h, T0CMPB, Offset 54h, T1CMPA, Offset 5Ah,
T1CMPB, Offset 5Ch, T2CMPA, Offset 62h) . . . . . . . . . . . . . . . . 8-7
(D0CON, Offset CAh, D1CON, Offset DAh) . . . . . . . . . . . . . . . . . 9-3
(D0TC, Offset C8h, D1TC, Offset D8h) . . . . . . . . . . . . . . . . . . . . . 9-6
(D0DSTH, Offset C6h, D1DSTH, Offset D6h) . . . . . . . . . . . . . . . . 9-7
(D0DSTL, Offset C4h, D1DSTL, Offset D4h) . . . . . . . . . . . . . . . . 9-8
(D0SRCH, Offset C2h, D1SRCH, Offset D2h) . . . . . . . . . . . . . . . 9-9
(D0SRCL, Offset C0h, D1SRCL, Offset D0h) . . . . . . . . . . . . . . . 9-10
(SP0CT/SP1CT, Offset 80h/10h) . . . . . . . . . . . . . . . . . . . . . . . . 10-5
(SP0STS/SP1STS, Offset 82h/12h) . . . . . . . . . . . . . . . . . . . . . . 10-9
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