AM186ES Advanced Micro Devices, AM186ES Datasheet - Page 6

• Manufacturer Part Number: AM186ES
• Description: microcontrollers provide a low-cost/ high-performance solution for embedded system designers who wish to use the x86 architecture.
• Manufacturer: Advanced Micro Devices

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CHAPTER 5
CHAPTER 6
CHAPTER 7
4.2
CHIP SELECT UNIT
5.1
5.2
5.3
5.4
5.5
6.1
INTERRUPT CONTROL UNIT
7.1
7.2
7.3
7.4
REFRESH CONTROL UNIT
INITIALIZATION AND PROCESSOR RESET . . . . . . . . . . . . . . . . . . . . . 4-8
OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
CHIP SELECT TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
READY AND WAIT-STATE PROGRAMMING . . . . . . . . . . . . . . . . . . . . . 5-2
CHIP SELECT OVERLAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
CHIP SELECT REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.5.1 Upper Memory Chip Select Register (UMCS, Offset A0h) . . . . . . 5-4
5.5.2 Low Memory Chip Select Register (LMCS, Offset A2h) . . . . . . . . 5-6
5.5.3 Midrange Memory Chip Select Register (MMCS, Offset A6h) . . . 5-8
5.5.4 PCS and MCS Auxiliary Register (MPCS, Offset A8h) . . . . . . . . 5-10
5.5.5 Peripheral Chip Select Register (PACS, Offset A4h) . . . . . . . . . 5-12
OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.1.1 Memory Partition Register (MDRAM, Offset E0h) . . . . . . . . . . . . 6-1
6.1.2 Clock Prescaler Register (CDRAM, Offset E2h) . . . . . . . . . . . . . . 6-2
6.1.3 Enable RCU Register (EDRAM, Offset E4h) . . . . . . . . . . . . . . . . 6-2
6.1.4 Watchdog Timer Control Register (WDTCON, Offset E6h). . . . . . 6-3
OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.1.1 Definitions of Interrupt Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.1.2 Interrupt Conditions and Sequence . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7.1.3 Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7.1.4 Software Exceptions, Traps, and NMI . . . . . . . . . . . . . . . . . . . . . . 7-7
7.1.5 Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
7.1.6 Interrupt Controller Reset Conditions . . . . . . . . . . . . . . . . . . . . . . 7-9
MASTER MODE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.2.1 Fully Nested Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.2.2 Cascade Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
7.2.3 Special Fully Nested Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
7.2.4 Operation in a Polled Environment . . . . . . . . . . . . . . . . . . . . . . . 7-12
7.2.5 End-of-Interrupt Write to the EOI Register . . . . . . . . . . . . . . . . . 7-12
MASTER MODE INTERRUPT CONTROLLER REGISTERS . . . . . . . . 7-13
7.3.1 INT0 and INT1 Control Registers
7.3.2 INT2 and INT3 Control Registers
7.3.3 INT4 Control Register (I4CON, Offset 40h). . . . . . . . . . . . . . . . . 7-16
7.3.4 Timer and DMA Interrupt Control Registers
7.3.5 Serial Port 0/1 Interrupt Control Registers
7.3.6 Interrupt Status Register (INTSTS, Offset 30h). . . . . . . . . . . . . . 7-19
7.3.7 Interrupt Request Register (REQST, Offset 2Eh) . . . . . . . . . . . . 7-20
7.3.8 Interrupt In-Service Register (INSERV, Offset 2Ch) . . . . . . . . . . 7-22
7.3.9 Priority Mask Register (PRIMSK, Offset 2Ah) . . . . . . . . . . . . . . . 7-23
7.3.10 Interrupt Mask Register (IMASK, Offset 28h) . . . . . . . . . . . . . . . 7-24
7.3.11 Poll Status Register (POLLST, Offset 26h) . . . . . . . . . . . . . . . . . 7-25
7.3.12 Poll Register (POLL, Offset 24h) . . . . . . . . . . . . . . . . . . . . . . . . . 7-26
7.3.13 End-of-Interrupt Register (EOI, Offset 22h). . . . . . . . . . . . . . . . . 7-27
SLAVE MODE OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28
7.4.1 Slave Mode Interrupt Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28
7.4.2 Slave Mode Interrupt Controller Registers . . . . . . . . . . . . . . . . . 7-28
(I0CON, Offset 38h, I1CON, Offset 3Ah). . . . . . . . . . . . . . . . . . . 7-14
(I2CON, Offset 3Ch, I3CON, Offset 3Eh) . . . . . . . . . . . . . . . . . . 7-15
(TCUCON, Offset 32h, DMA0CON/INT5CON, Offset 34h,
DMA1CON/INT6CON, Offset 36h) . . . . . . . . . . . . . . . . . . . . . . . 7-17
(SP0CON/SP1CON, Offset 44h/42h) . . . . . . . . . . . . . . . . . . . . . 7-18
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