AM186ES Advanced Micro Devices, AM186ES Datasheet - Page 90

• Manufacturer Part Number: AM186ES
• Description: microcontrollers provide a low-cost/ high-performance solution for embedded system designers who wish to use the x86 architecture.
• Manufacturer: Advanced Micro Devices

7.1.1.2
7.1.1.3
7.1.1.4
7.1.1.5
7-2
Software exceptions, internal peripherals, and non-cascaded external interrupts supply the
interrupt type through the internal interrupt controller.
Cascaded external interrupts and slave-mode external interrupts get the interrupt type from
the external interrupt controller by means of interrupt acknowledge cycles on the bus.
Interrupt Vector Table
The interrupt vector table is a memory area of 1 Kbyte beginning at address 00000h that
contains up to 256 four-byte address pointers containing the address for the interrupt service
routine for each possible interrupt type. For each interrupt, an 8-bit interrupt type identifies
the appropriate interrupt vector table entry.
Interrupts 00h to 1Fh are reserved. See Table 7-1.
The processor calculates the index to the interrupt vector table by shifting the interrupt type
left two bits (multiplying by 4).
Maskable and Nonmaskable Interrupts
Interrupt types 08h through 1Fh are maskable. Of these, only 08h through 14h are actually
in use (see Table 7-1). The maskable interrupts are enabled and disabled by the interrupt
enable flag (IF) in the processor status flags, but the INT command can execute any interrupt
regardless of the setting of IF.
Interrupt types 00h through 07h and all software interrupts (the INT instruction) are
nonmaskable. The nonmaskable interrupts are not affected by the setting of the IF flag.
The Am186ES and Am188ES microcontrollers provide two methods for masking and
unmasking the maskable interrupt sources. Each interrupt source has an interrupt control
register that contains a mask bit specific to that interrupt. In addition, the interrupt mask
register is provided as a single source to access all of the mask bits.
If the interrupt mask register is written while interrupts are enabled, it is possible that an
interrupt could occur while the register is in an undefined state. This can cause interrupts
to be accepted even though they were masked both before and after the write to the interrupt
mask register. Therefore, the interrupt mask register should only be written when interrupts
are disabled. Mask bits in the individual interrupt control registers can be written while
interrupts are enabled, and there will be no erroneous interrupt operation.
Interrupt Enable Flag (IF)
The interrupt enable flag (IF) is part of the processor status flags (see Section 2.1.1 on
page 2-2). If IF is set to 1, maskable interrupts are enabled and can cause processor
interrupts. (Individual maskable interrupts can still be disabled by means of the mask bit in
each control register.)
If IF is set to 0, all maskable interrupts are disabled.
The IF flag does not affect the NMI or software exception interrupts (interrupt types 00h to
07h), and it does not affect the execution of any interrupt through the INT instruction.
Interrupt Mask Bit
Each of the interrupt control registers for the maskable interrupts contains a mask bit (MSK).
If MSK is set to 1 for a particular interrupt, that interrupt is disabled regardless of the IF
setting.
Interrupt Control Unit