AM186ES Advanced Micro Devices, AM186ES Datasheet - Page 98

• Manufacturer Part Number: AM186ES
• Description: microcontrollers provide a low-cost/ high-performance solution for embedded system designers who wish to use the x86 architecture.
• Manufacturer: Advanced Micro Devices

7.2
7.2.1
Figure 7-2
7-10
Interrupt Source
Interrupt Source
MASTER MODE OPERATION
This section describes master mode operation of the internal interrupt controller. See
Section 7.4 on page 7-28 for a description of slave mode operation.
Eight pins are provided for external interrupt sources. One of these pins is NMI, the
nonmaskable interrupt. NMI is generally used for unusual events like power failure. The
other seven pins can be configured in any of the following ways:
The basic modes of operation of the interrupt controller in master mode are similar to the
82C59A. The interrupt controller responds identically to internal interrupts in all three
modes, the difference is only in the interpretation of function of the five external interrupt
pins. The interrupt controller is set into one of these modes by programming the correct
bits in the INT0 and INT1 control registers. The modes of interrupt controller operation are
fully nested mode, cascade mode, special fully nested mode, and polled mode.
Fully Nested Mode
In fully nested mode, seven pins are used as direct interrupt requests as in Figure 7-2. The
interrupt types for these seven inputs are generated internally. An in-service bit is provided
for every interrupt source. If a lower-priority device requests an interrupt while the in-service
bit (IS) is set for a high priority interrupt, no interrupt is generated by the interrupt controller.
In addition, if another interrupt request occurs from the same interrupt source while the in-
service bit is set, no interrupt is generated by the interrupt controller. This allows interrupt
service routines operating with interrupts enabled to be suspended only by interrupts of
equal or higher priority than the in-service interrupt.
When an interrupt service routine is completed, the proper IS bit must be reset by writing
the EOI type to the EOI register. This is required to allow subsequent interrupts from this
interrupt source and to allow servicing of lower-priority interrupts. A write to the EOI register
should be executed at the end of the interrupt service routine just before the return from
interrupt instruction.
Fully Nested (Direct) Mode Interrupt Controller Connections
Fully nested mode—seven interrupt lines with internally-generated interrupt types
Cascade mode one—an interrupt line and interrupt acknowledge line pair with externally-
generated interrupt types, plus five interrupt input lines with internally-generated types
Cascade mode two—two pairs of interrupt and interrupt acknowledge lines with
externally-generated interrupt types, and three interrupt input lines (INT6–INT4) with
internally-generated type
INT5
INT6
Microcontroller
or Am188ES
Am186ES
Interrupt Control Unit
INT0
INT1
INT2
INT3
INT4
Interrupt Source
Interrupt Source
Interrupt Source
Interrupt Source
Interrupt Source