AM186ES Advanced Micro Devices, AM186ES Datasheet - Page 145

• Manufacturer Part Number: AM186ES
• Description: microcontrollers provide a low-cost/ high-performance solution for embedded system designers who wish to use the x86 architecture.
• Manufacturer: Advanced Micro Devices

Figure 9-9
9.4.2
9.4.3
9.4.4
(Second case)
(First case)
CLKOUT
DRQ
DRQ
Destination Synchronized DMA Transfers
Notes:
1. This destination-synchronized transfer is not followed immediately by another DMA transfer.
2. This destination-synchronized transfer is immediately followed by another DMA transfer because
DMA Acknowledge
No explicit DMA acknowledge signal is provided. Since both source and destination
registers are maintained, a read from a requesting source or a write to a requesting
destination should be used as the DMA acknowledge signal. Since the chip-select lines
can be programmed to be active for a given block of memory or I/O space, and the DMA
source and destination address registers can be programmed to point to the same given
block, a chip-select line could be used to indicate a DMA acknowledge.
DMA Priority
The DMA channels can be programmed so that one channel is always given priority over
the other, or they can be programmed to alternate cycles when both have DMA requests
pending (see Section 9.3.1, bit 5, the P bit). DMA cycles always have priority over internal
CPU cycles except between locked memory accesses or word accesses to odd memory
locations. However, an external bus hold takes priority over an internal DMA cycle.
Because an interrupt request cannot suspend a DMA operation and the CPU cannot access
memory during a DMA cycle, interrupt latency time suffers during sequences of continuous
DMA cycles. An NMI request, however, causes all internal DMA activity to halt. This allows
the CPU to respond quickly to the NMI request.
DMA is also suspended during LOCKED bus cycles or during bus holds.
DMA Programming
DMA cycles occur whenever the ST bit of the control register is set. If synchronized transfers
are programmed, a DRQ must also be generated. Therefore, the source and destination
transfer address registers and the transfer count register (if used) must be programmed
before the ST bit is set.
Each DMA register can be modified while the channel is operating. If the CHG bit is set to
0 when the control register is written, the ST bit of the control register will not be modified
DRQ is not deasserted soon enough.
T1
Fetch Cycle
T2
T3
DMA Controller
T4
T1
T2
Deposit Cycle
T3
1
2
T4
TI
TI
9-13