AM186ES Advanced Micro Devices, AM186ES Datasheet - Page 190

• Manufacturer Part Number: AM186ES
• Description: microcontrollers provide a low-cost/ high-performance solution for embedded system designers who wish to use the x86 architecture.
• Manufacturer: Advanced Micro Devices

RDR bit (Receive Data Ready) 10-9
registers
I-6
Clock Prescaler (CDRAM, Offset E2h) 6-2
DMA 0 Control (D0CON, Offset CAh) 9-3
DMA 0 Destination Address High (D0DSTH,
DMA 0 Destination Address Low (D0DSTL,
DMA 0 Interrupt Control (DMA0CON,
DMA 0 Source Address High (D0SRCH,
DMA 0 Source Address Low (D0SRCL,
DMA 0 Transfer Count (D0TC, Offset C8h) 9-6
DMA 1 Control (D1CON, Offset DAh) 9-3
DMA 1 Destination Address High (D1DSTH,
DMA 1 Destination Address Low (D1DSTL,
DMA 1 Interrupt Control (DMA1CON,
DMA 1 Source Address High (D1SRCH,
DMA 1 Source Address Low (D1SRCL,
DMA 1 Transfer Count (D1TC, Offset D8h) 9-6
Enable RCU (EDRAM, Offset E4h) 6-2
End-of-Interrupt (EOI, Offset 22h) 7-27
In-Service (INSERV, Offset 2Ch) 7-22, 7-32
INT0 Control (INT0, Offset 38h)
INT1 Control (INT1, Offset 3Ah)
INT2 Control (INT2, Offset 3Ch)
INT3 Control (INT3, Offset 3Eh)
INT4 Control (INT4, Offset 40h)
Interrupt Mask (IMASK, Offset 28h) 7-24, 7-34
Interrupt Request (REQST, Offset 2Eh) 7-20, 7-31
Interrupt Status (INSTS, Offset 30h) 7-19
Interrupt Status (INTSTS, Offset 30h) 7-30
Interrupt Vector (INTVEC, Offset 20h) 7-36
Low Memory Chip Select (LMCS, Offset A2h) 5-6
Memory Partition (MDRAM, Offset E0h) 6-1
Midrange Memory Chip Select (MMCS,
Master mode
Master mode
Master mode
Master mode
Master mode
Offset C6h) 9-7
Offset C4h) 9-8
Offset 34h) 7-17, 7-29
Offset C2h) 9-9
Offset C0h) 9-10
Offset D6h) 9-7
Offset D4h) 9-8
Offset 36h) 7-17, 7-29
Offset D2h) 9-9
Offset D0h) 9-10
Offset A6h) 5-8
7-14
7-14
7-15
7-15
7-16
Index
PCS and MCS Auxiliary (MPCS, Offset A8h) 5-10
Peripheral Chip Select (PACS, Offset A4h) 5-12
Peripheral Control Block Relocation (RELREG,
PIO Data 0 (PDATA0, Offset 74h) 11-5
PIO Data 1 (PDATA1, Offset 7Ah) 11-5
PIO Direction 0 (PDIR0, Offset 72h) 11-4
PIO Direction 1 (PDIR1, Offset 78h) 11-4
PIO Mode 0 (PIOMODE0, Offset 70h) 11-3
PIO Mode 1 (PIOMODE1, Offset 76h) 11-3
Poll (POLL, Offset 24h) 7-26
Poll Status (POLLST, Offset 26h) 7-25
Priority Mask (PRIMSK, Offset 2Ah) 7-23, 7-33
Processor Release Level (PRL, Offset F4) 4-5
Reset Configuration (RESCON, Offset F6h) 4-4
Serial Port 0 Control (SP0CT, Offset 80h) 10-5
Serial Port 0 Status (SP0STS, Offset 82h) 10-9
Serial Port 1 Control (SP1CT, Offset 10h) 10-5
Serial Port 1 Status (SP1STS, Offset 12h) 10-9
Serial Port Baud Rate Divisor (SPBAUD,
Serial Port Interrupt Control (SPICON, Offset 44h)
Serial Port Receive Data (SPRD, Offset 86h) 10-12
Serial Port Transmit (SPTD, Offset 84h) 10-11
Specific End-of-Interrupt (EOI, OFfset 22h) 7-35
System Configuration Register (SYSCON,
Timer 0 Count (T0CNT, Offset 50h) 8-6
Timer 0 Interrupt Control (T0INTCON,
Timer 0 Maxcount Compare A (T0CMPA,
Timer 0 Maxcount Compare B (T0CMPB,
Timer 0 Mode and Control (T0CON, Offset 56h) 8-3
Timer 1 Count (T1CNT, Offset 58h) 8-6
Timer 1 Interrupt Control (T1INTCON,
Timer 1 Maxcount Compare A (T1CMPA,
Timer 1 Maxcount Compare B (T1CMPB,
Timer 1 Mode and Control (T1CON, Offset 5Eh) 8-3
Timer 2 Count (T2CNT, Offset 60h) 8-6
Timer 2 Interrupt Control (T2INTCON,
Master mode
Offset FEh) 4-3
Offset 88h) 10-13
Offset F0h) 4-7
Offset 32h) 7-29
Offset 52h) 8-7
Offset 54h) 8-7
Offset 38h) 7-29
Offset 5Ah) 8-7
Offset 5Ch) 8-7
Offset 3Ah) 7-29
7-18