AM186ES Advanced Micro Devices, AM186ES Datasheet - Page 125

• Manufacturer Part Number: AM186ES
• Description: microcontrollers provide a low-cost/ high-performance solution for embedded system designers who wish to use the x86 architecture.
• Manufacturer: Advanced Micro Devices

8.1
8.2
Figure 8-1
CHAPTER
8
TIMER CONTROL UNIT
OVERVIEW
There are three 16-bit programmable timers in the Am186ES and Am188ES
microcontrollers. Timers 0 and 1 are highly versatile and are each connected to two external
pins (each one has an input and an output). These two timers can be used to count or time
external events, or they can be used to generate nonrepetitive or variable-duty-cycle
waveforms.
Timer 2 is not connected to any external pins. It can be used for real-time coding and
time-delay applications. It can also be used as a prescale to timer 0 and timer 1 or as a
DMA request source.
PULSE WIDTH DEMODULATION
For many applications, such as bar-code reading, it is necessary to measure the width of
a signal in both its High and Low phases. The Am186ES and Am188ES microcontrollers
provide a pulse-width demodulation (PWD) option to fulfill this need. The PWD bit in the
system configuration register (SYSCON) enables the PWD option. Please note that the
Am186ES and Am188ES microcontrollers do not support analog-to-digital conversion.
In PWD mode, TMRIN0, TMRIN1, INT2, and INT4 are configured internal to the
microcontroller to support the detection of rising and falling edges on the PWD input pin
(INT2/INTA0/PWD) and to enable either timer 0 when the signal is High or timer 1 when
the signal is Low. The INT4, TMRIN0, and TMRIN1 pins are not used in PWD mode and
so are available for use as PIOs.
The following diagram shows the behavior of a system for a typical waveform.
Typical Waveform Behavior
The interrupt service routine (ISR) for the INT2 and INT4 interrupts should examine the
current count of the associated timer, timer 1 for INT2 and timer 0 for INT4, in order to
determine the pulse width. The ISR should then reset the timer count register in preparation
for the next pulse.
Since the timers count at one quarter of the processor clock rate, this determines the
maximum resolution that can be obtained. Further, in applications where the pulse width
may be short, it may be necessary to poll the INT2 and INT4 request bits in the interrupt
request register in order to avoid the overhead involved in taking and returning from an
interrupt. Overflow conditions, where the pulse width is greater than the maximum count
of the timer, can be detected by monitoring the Maximum Count (MC) bit in the associated
timer or by setting the INT bit to enable timer interrupt requests.
INT2
INT4
Timer Control Unit
INT2 Ints generated
TMR1 enabled
TMR0 enabled
8-1