AM186ES Advanced Micro Devices, AM186ES Datasheet - Page 152

• Manufacturer Part Number: AM186ES
• Description: microcontrollers provide a low-cost/ high-performance solution for embedded system designers who wish to use the x86 architecture.
• Manufacturer: Advanced Micro Devices

When a DMA channel is being used for serial port transmits or receives, the DMA request
is generated internally. The corresponding external DMA request signals, DRQ0 or DRQ1,
are not active for serial port DMA transfers.
Bit 12: Receive Status Interrupt Enable (RSIE)—This bit enables the serial port to
generate an interrupt request when an exception occurs during data reception. When this
bit is set, interrupt requests are generated for the error conditions reported in the serial port
status register (BRK0, BRK1, OER, PER, FER).
Bit 11: Send Break (BRK)—When this bit is set, the TXD pin is driven Low regardless of
the data being shifted out of the transmit register.
A short break, as reported by the BRK0 bit in the status register, is a continuous Low on
the TXD output for a duration of more than one frame transmission time M, where M = start
bit + data bits (+ parity bit)+ stop bit. The transmitter can be used to time the break by
setting the BRK bit when the transmitter is empty (indicated by the TEMT bit of the serial
port status register), writing the serial port transmit register with data, then waiting until the
TEMT bit is again set before resetting the BRK bit.
A long break, as reported by the BRK1 bit in the status register, is a continuous Low on the
TXD output for a duration of more than two frame transmission times plus the transmission
time for three additional bits (2M+3). The transmitter can be used to time the break as
follows:
1. Wait for the TEMT bit in the status register to be set.
2. Set the BRK bit.
3. Perform two sequential writes to the transmit register.
4. Wait for the TEMT bit in the status register to be set again.
5. Write a character with the low nibble zeroed and the high nibble High (for example, F0h).
6. Clear the BRK bit. The character being transmitted continues to hold the TXD pin Low
for the required additional 3-bit transmission time.
Note: The transmitter can only be used to time the break if hardware flow control is
disabled. If flow control is enabled, setting the BRK bit will still force the TXD line Low, but
the receiving device may deassert the CTS input, inhibiting the clocking out of the character
in the transmit data register.
Bit 10: Transmit Bit 8 (TB8)—This bit is transmitted as the ninth data bit in modes 2 and
3 (see the mode field description). This bit is not buffered and is cleared after every
transmission. In order to transmit a character with the 8th data bit High, the following protocol
should be followed:
1. Wait for the TEMT bit in the status register to become set.
2. Write the control register with this bit set.
3. Write the character to be transmitted.
Bit 9: Flow Control Enable (FC)—When this bit is 1, hardware flow control is enabled for
the associated serial port. When this bit is 0, hardware flow control is disabled for the
associated serial port. The nature of the flow control signals is determined by the setting
of the ENRX0/ENRX1 and RTS0/RTS1 bits in the AUXCON register. See the discussion
of the AUXCON register and Section 10.1.1 on page 10-1 for more information. If this bit
is 1 for serial port 0, the associated pins are used as flow control signals, overriding their
function as Peripheral Chip Select signals. This bit is 0 after processor reset.
10-6
Asynchronous Serial Port