AM186ES Advanced Micro Devices, AM186ES Datasheet - Page 87

• Manufacturer Part Number: AM186ES
• Description: microcontrollers provide a low-cost/ high-performance solution for embedded system designers who wish to use the x86 architecture.
• Manufacturer: Advanced Micro Devices

6.1.4
Figure 6-4
Watchdog Timer Control Register
(WDTCON, Offset E6h)
The Watchdog Timer Control register is a combined status and control register through
which all watchdog timer functionality is implemented. The format of the watchdog timer
control register is shown in Figure 6-4.
The watchdog timer (WDT) is enabled out of reset and configured to system reset mode
with a maximum timeout count. The WDTCON register can be opened for a single write
following reset. To open the WDTCON register for writing, the keyed sequence of 3333h
followed by CCCCh must be written to the WDTCON register. The register can then be
written with the new configuration. Any number of processor cycles, including memory and
I/O reads and writes, can be inserted between the two halves of the key or between the
key and the writing of the new configuration as long as they do not access the WDTCON
register.
Note: The Watchdog Timer (WDT) is active after reset.
It is not possible to read the current count of the WDT, however it can be reset by writing
the keyed sequence of AAAAh followed by 5555h to the WDTCON register. Any number
of processor cycles, including memory and I/O reads and writes, can be inserted between
the two halves of the key as long as they do not access the WDTCON register. The current
count should be reset before modifying the WDT timeout period to ensure that an immediate
WDT timeout does not occur.
Watchdog Timer Control Register
The value of the WDTCON register at reset is C080h.
Bit 15: Watchdog Timer Enable (ENA)—When this bit is 1, the watchdog timer is enabled.
When this bit is 0, the watchdog timer is disabled. This bit is 1 after processor reset.
Bit 14: Watchdog Reset (WRST)—When this bit is 1, the processor generates a WDT
system reset when the WDT timeout count is reached. When this bit is 0, the processor
generates an NMI interrupt when the WDT timeout count is reached if the NMIFLAG bit is
0. If the NMIFLAG bit is 1, a WDT system reset is generated upon WDT timeout. This bit
is 1 after processor reset.
Bit 13: Reset Flag (RSTFLAG)—When this bit is 1, a watchdog timer reset event has
occurred. This bit is cleared by any keyed read or write to this register or by an externally
generated system reset. This bit is 0 after an external system reset or 1 after a WDT system
reset.
Bit 12: NMI Flag (NMIFLAG)—When this bit is 1, a watchdog timer NMI event has occurred.
This bit is cleared by any keyed write to this register. If this bit is set when a WDT timeout
event occurs, a WDT system reset will be generated regardless of the setting of the WRST
bit. This bit is 0 after processor reset.
ENA
15
WRST
RSTFLAG
NMIFLAG
Refresh Control Unit
TEST
Res.
7
COUNT
0
6-3