AM186ES Advanced Micro Devices, AM186ES Datasheet - Page 112

• Manufacturer Part Number: AM186ES
• Description: microcontrollers provide a low-cost/ high-performance solution for embedded system designers who wish to use the x86 architecture.
• Manufacturer: Advanced Micro Devices

7.3.10
Figure 7-13
7-24
Interrupt Mask Register
(IMASK, Offset 28h)
(Master Mode)
The Interrupt Mask register is a read/write register. Programming a bit in the Interrupt Mask
register has the effect of programming the MSK bit in the associated interrupt control
register. The format of the Interrupt Mask register is shown in Figure 7-13.
When a bit is set to 1 in this register, the corresponding interrupt source is masked off.
When the bit is set to 0, the interrupt source is enabled to generate an interrupt request.
Interrupt Mask Register
The IMASK register is set to 07FDh on reset.
Bits 15–11: Reserved
Bit 10: Serial Port 0 Interrupt Mask (SP0)— When set to 1, this bit indicates that the serial
port 0 interrupt is masked.
Bit 9: Serial Port 1 Interrupt Mask (SP1)—When set to 1, this bit indicates that the serial
port 1 interrupt is masked.
Bits 8–4: Interrupt Mask (INT4–INT0)—When set to 1, an INT4–INT0 bit indicates that
the corresponding interrupt is masked.
Bits 3–2: DMA Channel Interrupt Masks (D1/I6–D0/I5)—When set to 1, a D1/I6–D0/I5
bit indicates that the corresponding DMA or INT6/INT5 channel interrupt is masked.
Bit 1: Reserved
Bit 0: Timer Interrupt Mask (TMR)—When set to 1, this bit indicates that interrupt requests
from the timer control unit are masked.
15
Reserved
Interrupt Control Unit
SP0
SP1
I4
7
I3
I2
I1
I0
D1/I6
D0/I5
Res
TMR
0