AM186ES Advanced Micro Devices, AM186ES Datasheet - Page 136

• Manufacturer Part Number: AM186ES
• Description: microcontrollers provide a low-cost/ high-performance solution for embedded system designers who wish to use the x86 architecture.
• Manufacturer: Advanced Micro Devices

Table 9-2
9-4
Bit 13: Destination Increment (DINC)—When DINC is set to 1, the destination address
is automatically incremented after each transfer. The address increments by 1 or 2
depending on the byte/word bit (B/W, bit 0). The address remains constant if the increment
and decrement bits are set to the same value (00b or 11b).
Bit 12: Source Address Space Select (SM/IO)—When SM/IO is set to 1, the source
address is in memory space. When set to 0, the source address is in I/O space.
Bit 11: Source Decrement (SDEC)—When SDEC is set to 1, the source address is
automatically decremented after each transfer. The address decrements by 1 or 2,
depending on the byte/word bit (B/W, bit 0). The address remains constant if the increment
and decrement bits are set to the same value (00b or 11b).
Bit 10: Source Increment (SINC)—When SINC is set to 1, the source address is
automatically incremented after each transfer. The address increments by 1 or 2 depending
on the byte/word bit (B/W, bit 0). The address remains constant if the increment and
decrement bits are set to the same value (00b or 11b).
Bit 9: Terminal Count (TC)—The DMA decrements the transfer count for each DMA
transfer. When TC is set to 1, source or destination synchronized DMA transfers terminate
when the count reaches 0. When TC is set to 0, source or destination synchronized DMA
transfers do not terminate when the count reaches 0. Unsynchronized DMA transfers
always terminate when the count reaches 0, regardless of the setting of this bit.
Bit 8: Interrupt (INT)—When INT is set to 1, the DMA channel generates an interrupt
request on completion of the transfer count. The TC bit must also be set to generate an
interrupt.
Bits 7–6: Synchronization Type (SYN1–SYN0)—The SYN1–SYN0 bits select channel
synchronization as shown in Table 9-2. The value of this field is ignored if TDRQ (bit 4) is
set to 1. For more information on DMA synchronization, see Section 9.4 on page 9-11. This
field is 11b after processor reset.
Synchronization Type
Bit 5: Relative Priority (P)—When P is set to 1, it selects high priority for this channel
relative to the other channel during simultaneous transfers.
Bit 4: Timer 2 Synchronization (TDRQ)—When TDRQ is set to 1, it enables DMA requests
from timer 2. When set to 0, TDRQ disables DMA requests from timer 2.
Bit 3: External Interrupt Enable Bit (EXT)—This bit enables the external interrupt
functionality of the corresponding DRQ pin. If this bit is set to 1, the external pin is an INT
pin and requests on the pin are processed by the interrupt controller; the associated DMA
channel does not respond to changes on the DRQ pin. When this bit is set to 0, the pin
functions as a DRQ pin.
Bit 2: Change Start Bit (CHG)—This bit must be set to 1 during a write to allow modification
of the ST bit. When CHG is set to 0 during a write, ST is not altered when writing the control
word. This bit always reads as 0.
SYN1
0
0
1
1
SYN0
0
1
0
1
Sync Type
Unsynchronized
Source Synch
Destination Synch
Reserved
DMA Controller